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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2018 Spreadtrum Communications Inc.
* Copyright (C) 2018 Linaro Ltd.
*/
#include <linux/bitops.h>
#include <linux/gpio/driver.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/spinlock.h>
/* EIC registers definition */
#define SPRD_EIC_DBNC_DATA 0x0
#define SPRD_EIC_DBNC_DMSK 0x4
#define SPRD_EIC_DBNC_IEV 0x14
#define SPRD_EIC_DBNC_IE 0x18
#define SPRD_EIC_DBNC_RIS 0x1c
#define SPRD_EIC_DBNC_MIS 0x20
#define SPRD_EIC_DBNC_IC 0x24
#define SPRD_EIC_DBNC_TRIG 0x28
#define SPRD_EIC_DBNC_CTRL0 0x40
#define SPRD_EIC_LATCH_INTEN 0x0
#define SPRD_EIC_LATCH_INTRAW 0x4
#define SPRD_EIC_LATCH_INTMSK 0x8
#define SPRD_EIC_LATCH_INTCLR 0xc
#define SPRD_EIC_LATCH_INTPOL 0x10
#define SPRD_EIC_LATCH_INTMODE 0x14
#define SPRD_EIC_ASYNC_INTIE 0x0
#define SPRD_EIC_ASYNC_INTRAW 0x4
#define SPRD_EIC_ASYNC_INTMSK 0x8
#define SPRD_EIC_ASYNC_INTCLR 0xc
#define SPRD_EIC_ASYNC_INTMODE 0x10
#define SPRD_EIC_ASYNC_INTBOTH 0x14
#define SPRD_EIC_ASYNC_INTPOL 0x18
#define SPRD_EIC_ASYNC_DATA 0x1c
#define SPRD_EIC_SYNC_INTIE 0x0
#define SPRD_EIC_SYNC_INTRAW 0x4
#define SPRD_EIC_SYNC_INTMSK 0x8
#define SPRD_EIC_SYNC_INTCLR 0xc
#define SPRD_EIC_SYNC_INTMODE 0x10
#define SPRD_EIC_SYNC_INTBOTH 0x14
#define SPRD_EIC_SYNC_INTPOL 0x18
#define SPRD_EIC_SYNC_DATA 0x1c
/*
* The digital-chip EIC controller can support maximum 3 banks, and each bank
* contains 8 EICs.
*/
#define SPRD_EIC_MAX_BANK 3
#define SPRD_EIC_PER_BANK_NR 8
#define SPRD_EIC_DATA_MASK GENMASK(7, 0)
#define SPRD_EIC_BIT(x) ((x) & (SPRD_EIC_PER_BANK_NR - 1))
#define SPRD_EIC_DBNC_MASK GENMASK(11, 0)
/*
* The Spreadtrum EIC (external interrupt controller) can be used only in
* input mode to generate interrupts if detecting input signals.
*
* The Spreadtrum digital-chip EIC controller contains 4 sub-modules:
* debounce EIC, latch EIC, async EIC and sync EIC,
*
* The debounce EIC is used to capture the input signals' stable status
* (millisecond resolution) and a single-trigger mechanism is introduced
* into this sub-module to enhance the input event detection reliability.
* The debounce range is from 1ms to 4s with a step size of 1ms.
*
* The latch EIC is used to latch some special power down signals and
* generate interrupts, since the latch EIC does not depend on the APB clock
* to capture signals.
*
* The async EIC uses a 32k clock to capture the short signals (microsecond
* resolution) to generate interrupts by level or edge trigger.
*
* The EIC-sync is similar with GPIO's input function, which is a synchronized
* signal input register.
*/
enum sprd_eic_type {
SPRD_EIC_DEBOUNCE,
SPRD_EIC_LATCH,
SPRD_EIC_ASYNC,
SPRD_EIC_SYNC,
SPRD_EIC_MAX,
};
struct sprd_eic {
struct gpio_chip chip;
struct irq_chip intc;
void __iomem *base[SPRD_EIC_MAX_BANK];
enum sprd_eic_type type;
spinlock_t lock;
int irq;
};
struct sprd_eic_variant_data {
enum sprd_eic_type type;
u32 num_eics;
};
static const char *sprd_eic_label_name[SPRD_EIC_MAX] = {
"eic-debounce", "eic-latch", "eic-async",
"eic-sync",
};
static const struct sprd_eic_variant_data sc9860_eic_dbnc_data = {
.type = SPRD_EIC_DEBOUNCE,
.num_eics = 8,
};
static const struct sprd_eic_variant_data sc9860_eic_latch_data = {
.type = SPRD_EIC_LATCH,
.num_eics = 8,
};
static const struct sprd_eic_variant_data sc9860_eic_async_data = {
.type = SPRD_EIC_ASYNC,
.num_eics = 8,
};
static const struct sprd_eic_variant_data sc9860_eic_sync_data = {
.type = SPRD_EIC_SYNC,
.num_eics = 8,
};
static inline void __iomem *sprd_eic_offset_base(struct sprd_eic *sprd_eic,
unsigned int bank)
{
if (bank >= SPRD_EIC_MAX_BANK)
return NULL;
return sprd_eic->base[bank];
}
static void sprd_eic_update(struct gpio_chip *chip, unsigned int offset,
u16 reg, unsigned int val)
{
struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
void __iomem *base =
sprd_eic_offset_base(sprd_eic, offset / SPRD_EIC_PER_BANK_NR);
unsigned long flags;
u32 tmp;
spin_lock_irqsave(&sprd_eic->lock, flags);
tmp = readl_relaxed(base + reg);
if (val)
tmp |= BIT(SPRD_EIC_BIT(offset));
else
tmp &= ~BIT(SPRD_EIC_BIT(offset));
writel_relaxed(tmp, base + reg);
spin_unlock_irqrestore(&sprd_eic->lock, flags);
}
static int sprd_eic_read(struct gpio_chip *chip, unsigned int offset, u16 reg)
{
struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
void __iomem *base =
sprd_eic_offset_base(sprd_eic, offset / SPRD_EIC_PER_BANK_NR);
return !!(readl_relaxed(base + reg) & BIT(SPRD_EIC_BIT(offset)));
}
static int sprd_eic_request(struct gpio_chip *chip, unsigned int offset)
{
sprd_eic_update(chip, offset, SPRD_EIC_DBNC_DMSK, 1);
return 0;
}
static void sprd_eic_free(struct gpio_chip *chip, unsigned int offset)
{
sprd_eic_update(chip, offset, SPRD_EIC_DBNC_DMSK, 0);
}
static int sprd_eic_get(struct gpio_chip *chip, unsigned int offset)
{
struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
switch (sprd_eic->type) {
case SPRD_EIC_DEBOUNCE:
return sprd_eic_read(chip, offset, SPRD_EIC_DBNC_DATA);
case SPRD_EIC_ASYNC:
return sprd_eic_read(chip, offset, SPRD_EIC_ASYNC_DATA);
case SPRD_EIC_SYNC:
return sprd_eic_read(chip, offset, SPRD_EIC_SYNC_DATA);
default:
return -ENOTSUPP;
}
}
static int sprd_eic_direction_input(struct gpio_chip *chip, unsigned int offset)
{
/* EICs are always input, nothing need to do here. */
return 0;
}
static void sprd_eic_set(struct gpio_chip *chip, unsigned int offset, int value)
{
/* EICs are always input, nothing need to do here. */
}
static int sprd_eic_set_debounce(struct gpio_chip *chip, unsigned int offset,
unsigned int debounce)
{
struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
void __iomem *base =
sprd_eic_offset_base(sprd_eic, offset / SPRD_EIC_PER_BANK_NR);
u32 reg = SPRD_EIC_DBNC_CTRL0 + SPRD_EIC_BIT(offset) * 0x4;
u32 value = readl_relaxed(base + reg) & ~SPRD_EIC_DBNC_MASK;
value |= (debounce / 1000) & SPRD_EIC_DBNC_MASK;
writel_relaxed(value, base + reg);
return 0;
}
static int sprd_eic_set_config(struct gpio_chip *chip, unsigned int offset,
unsigned long config)
{
unsigned long param = pinconf_to_config_param(config);
u32 arg = pinconf_to_config_argument(config);
if (param == PIN_CONFIG_INPUT_DEBOUNCE)
return sprd_eic_set_debounce(chip, offset, arg);
return -ENOTSUPP;
}
static void sprd_eic_irq_mask(struct irq_data *data)
{
struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
u32 offset = irqd_to_hwirq(data);
switch (sprd_eic->type) {
case SPRD_EIC_DEBOUNCE:
sprd_eic_update(chip,
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