path: root/drivers/fpga/socfpga.c

/*
 * FPGA Manager Driver for Altera SOCFPGA
 *
 *  Copyright (C) 2013-2015 Altera Corporation
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program.  If not, see <http://www.gnu.org/licenses/>.
 */
#include <linux/completion.h>
#include <linux/delay.h>
#include <linux/fpga/fpga-mgr.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/pm.h>

/* Register offsets */
#define SOCFPGA_FPGMGR_STAT_OFST				0x0
#define SOCFPGA_FPGMGR_CTL_OFST					0x4
#define SOCFPGA_FPGMGR_DCLKCNT_OFST				0x8
#define SOCFPGA_FPGMGR_DCLKSTAT_OFST				0xc
#define SOCFPGA_FPGMGR_GPIO_INTEN_OFST				0x830
#define SOCFPGA_FPGMGR_GPIO_INTMSK_OFST				0x834
#define SOCFPGA_FPGMGR_GPIO_INTTYPE_LEVEL_OFST			0x838
#define SOCFPGA_FPGMGR_GPIO_INT_POL_OFST			0x83c
#define SOCFPGA_FPGMGR_GPIO_INTSTAT_OFST			0x840
#define SOCFPGA_FPGMGR_GPIO_RAW_INTSTAT_OFST			0x844
#define SOCFPGA_FPGMGR_GPIO_PORTA_EOI_OFST			0x84c
#define SOCFPGA_FPGMGR_GPIO_EXT_PORTA_OFST			0x850

/* Register bit defines */
/* SOCFPGA_FPGMGR_STAT register mode field values */
#define SOCFPGA_FPGMGR_STAT_POWER_UP				0x0 /*ramping*/
#define SOCFPGA_FPGMGR_STAT_RESET				0x1
#define SOCFPGA_FPGMGR_STAT_CFG					0x2
#define SOCFPGA_FPGMGR_STAT_INIT				0x3
#define SOCFPGA_FPGMGR_STAT_USER_MODE				0x4
#define SOCFPGA_FPGMGR_STAT_UNKNOWN				0x5
#define SOCFPGA_FPGMGR_STAT_STATE_MASK				0x7
/* This is a flag value that doesn't really happen in this register field */
#define SOCFPGA_FPGMGR_STAT_POWER_OFF				0x0

#define MSEL_PP16_FAST_NOAES_NODC				0x0
#define MSEL_PP16_FAST_AES_NODC					0x1
#define MSEL_PP16_FAST_AESOPT_DC				0x2
#define MSEL_PP16_SLOW_NOAES_NODC				0x4
#define MSEL_PP16_SLOW_AES_NODC					0x5
#define MSEL_PP16_SLOW_AESOPT_DC				0x6
#define MSEL_PP32_FAST_NOAES_NODC				0x8
#define MSEL_PP32_FAST_AES_NODC					0x9
#define MSEL_PP32_FAST_AESOPT_DC				0xa
#define MSEL_PP32_SLOW_NOAES_NODC				0xc
#define MSEL_PP32_SLOW_AES_NODC					0xd
#define MSEL_PP32_SLOW_AESOPT_DC				0xe
#define SOCFPGA_FPGMGR_STAT_MSEL_MASK				0x000000f8
#define SOCFPGA_FPGMGR_STAT_MSEL_SHIFT				3

/* SOCFPGA_FPGMGR_CTL register */
#define SOCFPGA_FPGMGR_CTL_EN					0x00000001
#define SOCFPGA_FPGMGR_CTL_NCE					0x00000002
#define SOCFPGA_FPGMGR_CTL_NCFGPULL				0x00000004

#define CDRATIO_X1						0x00000000
#define CDRATIO_X2						0x00000040
#define CDRATIO_X4						0x00000080
#define CDRATIO_X8						0x000000c0
#define SOCFPGA_FPGMGR_CTL_CDRATIO_MASK				0x000000c0

#define SOCFPGA_FPGMGR_CTL_AXICFGEN				0x00000100

#define CFGWDTH_16						0x00000000
#define CFGWDTH_32						0x00000200
#define SOCFPGA_FPGMGR_CTL_CFGWDTH_MASK				0x00000200

/* SOCFPGA_FPGMGR_DCLKSTAT register */
#define SOCFPGA_FPGMGR_DCLKSTAT_DCNTDONE_E_DONE			0x1

/* SOCFPGA_FPGMGR_GPIO_* registers share the same bit positions */
#define SOCFPGA_FPGMGR_MON_NSTATUS				0x0001
#define SOCFPGA_FPGMGR_MON_CONF_DONE				0x0002
#define SOCFPGA_FPGMGR_MON_INIT_DONE				0x0004
#define SOCFPGA_FPGMGR_MON_CRC_ERROR				0x0008
#define SOCFPGA_FPGMGR_MON_CVP_CONF_DONE			0x0010
#define SOCFPGA_FPGMGR_MON_PR_READY				0x0020
#define SOCFPGA_FPGMGR_MON_PR_ERROR				0x0040
#define SOCFPGA_FPGMGR_MON_PR_DONE				0x0080
#define SOCFPGA_FPGMGR_MON_NCONFIG_PIN				0x0100
#define SOCFPGA_FPGMGR_MON_NSTATUS_PIN				0x0200
#define SOCFPGA_FPGMGR_MON_CONF_DONE_PIN			0x0400
#define SOCFPGA_FPGMGR_MON_FPGA_POWER_ON			0x0800
#define SOCFPGA_FPGMGR_MON_STATUS_MASK				0x0fff

#define SOCFPGA_FPGMGR_NUM_SUPPLIES 3
#define SOCFPGA_RESUME_TIMEOUT 3

/* In power-up order. Reverse for power-down. */
static const char *supply_names[SOCFPGA_FPGMGR_NUM_SUPPLIES] __maybe_unused = {
	"FPGA-1.5V",
	"FPGA-1.1V",
	"FPGA-2.5V",
};

struct socfpga_fpga_priv {
	void __iomem *fpga_base_addr;
	void __iomem *fpga_data_addr;
	struct completion status_complete;
	int irq;
};

struct cfgmgr_mode {
	/* Values to set in the CTRL register */
	u32 ctrl;

	/* flag that this table entry is a valid mode */
	bool valid;
};

/* For SOCFPGA_FPGMGR_STAT_MSEL field */
static struct cfgmgr_mode cfgmgr_modes[] = {
	[MSEL_PP16_FAST_NOAES_NODC] = { CFGWDTH_16 | CDRATIO_X1, 1 },
	[MSEL_PP16_FAST_AES_NODC] =   { CFGWDTH_16 | CDRATIO_X2, 1 },
	[MSEL_PP16_FAST_AESOPT_DC] =  { CFGWDTH_16 | CDRATIO_X4, 1 },
	[MSEL_PP16_SLOW_NOAES_NODC] = { CFGWDTH_16 | CDRATIO_X1, 1 },
	[MSEL_PP16_SLOW_AES_NODC] =   { CFGWDTH_16 | CDRATIO_X2, 1 },
	[MSEL_PP16_SLOW_AESOPT_DC] =  { CFGWDTH_16 | CDRATIO_X4, 1 },
	[MSEL_PP32_FAST_NOAES_NODC] = { CFGWDTH_32 | CDRATIO_X1, 1 },
	[MSEL_PP32_FAST_AES_NODC] =   { CFGWDTH_32 | CDRATIO_X4, 1 },
	[MSEL_PP32_FAST_AESOPT_DC] =  { CFGWDTH_32 | CDRATIO_X8, 1 },
	[MSEL_PP32_SLOW_NOAES_NODC] = { CFGWDTH_32 | CDRATIO_X1, 1 },
	[MSEL_PP32_SLOW_AES_NODC] =   { CFGWDTH_32 | CDRATIO_X4, 1 },
	[MSEL_PP32_SLOW_AESOPT_DC] =  { CFGWDTH_32 | CDRATIO_X8, 1 },
};

static u32 socfpga_fpga_readl(struct socfpga_fpga_priv *priv, u32 reg_offset)
{
	return readl(priv->fpga_base_addr + reg_offset);
}

static void socfpga_fpga_writel(struct socfpga_fpga_priv *priv, u32 reg_offset,
				u32 value)
{
	writel(value, priv->fpga_base_addr + reg_offset);
}

static u32 socfpga_fpga_raw_readl(struct socfpga_fpga_priv *priv,
				  u32 reg_offset)
{
	return __raw_readl(priv->fpga_base_addr + reg_offset);
}

static void socfpga_fpga_raw_writel(struct socfpga_fpga_priv *priv,
				    u32 reg_offset, u32 value)
{
	__raw_writel(value, priv->fpga_base_addr + reg_offset);
}

static void socfpga_fpga_data_writel(struct socfpga_fpga_priv *priv, u32 value)
{
	writel(value, priv->fpga_data_addr);
}

static inline void socfpga_fpga_set_bitsl(struct socfpga_fpga_priv *priv,
					  u32 offset, u32 bits)
{
	u32 val;

	val = socfpga_fpga_readl(priv, offset);
	val |= bits;
	socfpga_fpga_writel(priv, offset, val);
}

static inline void socfpga_fpga_clr_bitsl(struct socfpga_fpga_priv *priv,
					  u32 offset, u32 bits)
{
	u32 val;

	val = socfpga_fpga_readl(priv, offset);
	val &= ~bits;
	socfpga_fpga_writel(priv, offset, val);
}

static u32 socfpga_fpga_mon_status_get(struct socfpga_fpga_priv *priv)
{
	return socfpga_fpga_readl(priv, SOCFPGA_FPGMGR_GPIO_EXT_PORTA_OFST) &
		SOCFPGA_FPGMGR_MON_STATUS_MASK;
}

static u32 socfpga_fpga_state_get(struct socfpga_fpga_priv *priv)
{
	u32 status = socfpga_fpga_mon_status_get(priv);

	if ((status & SOCFPGA_FPGMGR_MON_FPGA_POWER_ON) == 0)
		return SOCFPGA_FPGMGR_STAT_POWER_OFF;

	return socfpga_fpga_readl(priv, SOCFPGA_FPGMGR_STAT_OFST) &
		SOCFPGA_FPGMGR_STAT_STATE_MASK;
}

static void socfpga_fpga_clear_done_status(struct socfpga_fpga_priv *priv)
{
	socfpga_fpga_writel(priv, SOCFPGA_FPGMGR_DCLKSTAT_OFST,
			    SOCFPGA_FPGMGR_DCLKSTAT_DCNTDONE_E_DONE);
}

/*
 * Set the DCLKCNT, wait for DCLKSTAT to report the count completed, and clear
 * the complete status.
 */
static int socfpga_fpga_dclk_set_and_wait_clear(struct socfpga_fpga_priv *priv,
						u32 count)
{
	int timeout = 2;
	u32 done;

	/* Clear any existing DONE status. */
	if (socfpga_fpga_readl(priv, SOCFPGA_FPGMGR_DCLKSTAT_OFST))
		socfpga_fpga_clear_done_status(priv);

	/* Issue the DCLK count. */
	socfpga_fpga_writel(priv, SOCFPGA_FPGMGR_DCLKCNT_OFST, count);

	/* Poll DCLKSTAT to see if it completed in the timeout period. */
	do {
		done = socfpga_fpga_readl(priv, SOCFPGA_FPGMGR_DCLKSTAT_OFST);
		if (done == SOCFPGA_FPGMGR_DCLKSTAT_DCNTDONE_E_DONE) {
			socfpga_fpga_clear_done_status(priv);
			return 0;
		}
		udelay(1);
	} while (timeout--);

	return -ETIMEDOUT;
}

static int socfpga_fpga_wait_for_state(struct socfpga_fpga_priv *priv,
				       u32 state)
{
	int timeout = 2;

	/*
	 * HW doesn't support an interrupt for changes in state, so poll to see
	 * if it matches the requested state within the timeout period.
	 */
	do {
		if ((socfpga_fpga_state_get(priv) & state) != 0)
			return 0;
		msleep(20);
	} while (timeout--);

	return -ETIMEDOUT;
}

static void socfpga_fpga_enable_irqs(struct socfpga_fpga_priv *priv, u32 irqs)
{
	/* set irqs to level sensitive */
	socfpga_fpga_writel(priv, SOCFPGA_FPGMGR_GPIO_INTTYPE_LEVEL_OFST, 0);

	/* set interrupt polarity */
	socfpga_fpga_writel(priv, SOCFPGA_FPGMGR_GPIO_INT_POL_OFST, irqs);

	/* clear irqs */
	socfpga_fpga_writel(priv, SOCFPGA_FPGMGR_GPIO_PORTA_EOI_OFST, irqs);

	/* unmask interrupts */
	socfpga_fpga_writel(priv, SOCFPGA_FPGMGR_GPIO_INTMSK_OFST, 0);

	/* enable interrupts */
	socfpga_fpga_writel(priv, SOCFPGA_FPGMGR_GPIO_INTEN_OFST, irqs);
}

static void socfpga_fpga_disable_irqs(struct socfpga_fpga_priv *priv)
{