path: root/drivers/edac/ppc4xx_edac.c

/*
 * Copyright (c) 2008 Nuovation System Designs, LLC
 *   Grant Erickson <gerickson@nuovations.com>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; version 2 of the
 * License.
 *
 */

#include <linux/edac.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/of_platform.h>
#include <linux/types.h>

#include <asm/dcr.h>

#include "edac_core.h"
#include "ppc4xx_edac.h"

/*
 * This file implements a driver for monitoring and handling events
 * associated with the IMB DDR2 ECC controller found in the AMCC/IBM
 * 405EX[r], 440SP, 440SPe, 460EX, 460GT and 460SX.
 *
 * As realized in the 405EX[r], this controller features:
 *
 *   - Support for registered- and non-registered DDR1 and DDR2 memory.
 *   - 32-bit or 16-bit memory interface with optional ECC.
 *
 *     o ECC support includes:
 *
 *       - 4-bit SEC/DED
 *       - Aligned-nibble error detect
 *       - Bypass mode
 *
 *   - Two (2) memory banks/ranks.
 *   - Up to 1 GiB per bank/rank in 32-bit mode and up to 512 MiB per
 *     bank/rank in 16-bit mode.
 *
 * As realized in the 440SP and 440SPe, this controller changes/adds:
 *
 *   - 64-bit or 32-bit memory interface with optional ECC.
 *
 *     o ECC support includes:
 *
 *       - 8-bit SEC/DED
 *       - Aligned-nibble error detect
 *       - Bypass mode
 *
 *   - Up to 4 GiB per bank/rank in 64-bit mode and up to 2 GiB
 *     per bank/rank in 32-bit mode.
 *
 * As realized in the 460EX and 460GT, this controller changes/adds:
 *
 *   - 64-bit or 32-bit memory interface with optional ECC.
 *
 *     o ECC support includes:
 *
 *       - 8-bit SEC/DED
 *       - Aligned-nibble error detect
 *       - Bypass mode
 *
 *   - Four (4) memory banks/ranks.
 *   - Up to 16 GiB per bank/rank in 64-bit mode and up to 8 GiB
 *     per bank/rank in 32-bit mode.
 *
 * At present, this driver has ONLY been tested against the controller
 * realization in the 405EX[r] on the AMCC Kilauea and Haleakala
 * boards (256 MiB w/o ECC memory soldered onto the board) and a
 * proprietary board based on those designs (128 MiB ECC memory, also
 * soldered onto the board).
 *
 * Dynamic feature detection and handling needs to be added for the
 * other realizations of this controller listed above.
 *
 * Eventually, this driver will likely be adapted to the above variant
 * realizations of this controller as well as broken apart to handle
 * the other known ECC-capable controllers prevalent in other 4xx
 * processors:
 *
 *   - IBM SDRAM (405GP, 405CR and 405EP) "ibm,sdram-4xx"
 *   - IBM DDR1 (440GP, 440GX, 440EP and 440GR) "ibm,sdram-4xx-ddr"
 *   - Denali DDR1/DDR2 (440EPX and 440GRX) "denali,sdram-4xx-ddr2"
 *
 * For this controller, unfortunately, correctable errors report
 * nothing more than the beat/cycle and byte/lane the correction
 * occurred on and the check bit group that covered the error.
 *
 * In contrast, uncorrectable errors also report the failing address,
 * the bus master and the transaction direction (i.e. read or write)
 *
 * Regardless of whether the error is a CE or a UE, we report the
 * following pieces of information in the driver-unique message to the
 * EDAC subsystem:
 *
 *   - Device tree path
 *   - Bank(s)
 *   - Check bit error group
 *   - Beat(s)/lane(s)
 */

/* Preprocessor Definitions */

#define EDAC_OPSTATE_INT_STR		"interrupt"