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/*
* Intel MIC Platform Software Stack (MPSS)
*
* Copyright(c) 2014 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, version 2, as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* The full GNU General Public License is included in this distribution in
* the file called "COPYING".
*
* Intel MIC X100 DMA Driver.
*
* Adapted from IOAT dma driver.
*/
#include <linux/module.h>
#include <linux/io.h>
#include <linux/seq_file.h>
#include <linux/vmalloc.h>
#include "mic_x100_dma.h"
#define MIC_DMA_MAX_XFER_SIZE_CARD (1 * 1024 * 1024 -\
MIC_DMA_ALIGN_BYTES)
#define MIC_DMA_MAX_XFER_SIZE_HOST (1 * 1024 * 1024 >> 1)
#define MIC_DMA_DESC_TYPE_SHIFT 60
#define MIC_DMA_MEMCPY_LEN_SHIFT 46
#define MIC_DMA_STAT_INTR_SHIFT 59
/* high-water mark for pushing dma descriptors */
static int mic_dma_pending_level = 4;
/* Status descriptor is used to write a 64 bit value to a memory location */
enum mic_dma_desc_format_type {
MIC_DMA_MEMCPY = 1,
MIC_DMA_STATUS,
};
static inline u32 mic_dma_hw_ring_inc(u32 val)
{
return (val + 1) % MIC_DMA_DESC_RX_SIZE;
}
static inline u32 mic_dma_hw_ring_dec(u32 val)
{
return val ? val - 1 : MIC_DMA_DESC_RX_SIZE - 1;
}
static inline void mic_dma_hw_ring_inc_head(struct mic_dma_chan *ch)
{
ch->head = mic_dma_hw_ring_inc(ch->head);
}
/* Prepare a memcpy desc */
static inline void mic_dma_memcpy_desc(struct mic_dma_desc *desc,
dma_addr_t src_phys, dma_addr_t dst_phys, u64 size)
{
u64 qw0, qw1;
qw0 = src_phys;
qw0 |= (size >> MIC_DMA_ALIGN_SHIFT) << MIC_DMA_MEMCPY_LEN_SHIFT;
qw1 = MIC_DMA_MEMCPY;
qw1 <<= MIC_DMA_DESC_TYPE_SHIFT;
qw1 |= dst_phys;
desc->qw0 = qw0;
desc->qw1 = qw1;
}
/* Prepare a status desc. with @data to be written at @dst_phys */
static inline void mic_dma_prep_status_desc(struct mic_dma_desc *desc, u64 data,
dma_addr_t dst_phys, bool generate_intr)
{
u64 qw0, qw1;
qw0 = data;
qw1 = (u64) MIC_DMA_STATUS << MIC_DMA_DESC_TYPE_SHIFT | dst_phys;
if (generate_intr)
qw1 |= (1ULL << MIC_DMA_STAT_INTR_SHIFT);
desc->qw0 = qw0;
desc->qw1 = qw1;
}
static void mic_dma_cleanup(struct mic_dma_chan *ch)
{
struct dma_async_tx_descriptor *tx;
u32 tail;
u32 last_tail;
spin_lock(&ch->cleanup_lock);
tail = mic_dma_read_cmp_cnt(ch);
/*
* This is the barrier pair for smp_wmb() in fn.
* mic_dma_tx_submit_unlock. It's required so that we read the
* updated cookie value from tx->cookie.
*/
smp_rmb();
for (last_tail = ch->last_tail; tail != last_tail;) {
tx = &ch->tx_array[last_tail];
if (tx->cookie) {
dma_cookie_complete(tx);
if (tx->callback) {
tx->callback(tx->callback_param);
tx->callback = NULL;
}
}
last_tail = mic_dma_hw_ring_inc(last_tail);
}
/* finish all completion callbacks before incrementing tail */
smp_mb();
ch->last_tail = last_tail;
spin_unlock(&ch->cleanup_lock);
}
static u32 mic_dma_ring_count(u32 head, u32 tail)
{
u32 count;
if (head >= tail)
count = (tail - 0) + (MIC_DMA_DESC_RX_SIZE - head);
else
count = tail - head;
return count - 1;
}
/* Returns the num. of free descriptors on success, -ENOMEM on failure */
static int mic_dma_avail_desc_ring_space(struct mic_dma_chan *ch, int required)
{
struct device *dev = mic_dma_ch_to_device(ch);
u32 count;
count = mic_dma_ring_count(ch->head, ch->last_tail);
if (count < required) {
mic_dma_cleanup(ch);
count = mic_dma_ring_count(ch->head, ch->last_tail);
}
if (count < required) {
dev_dbg(dev, "Not enough desc space");
dev_dbg(dev, "%s %d required=%u, avail=%u\n",
__func__, __LINE__, required, count);
return -ENOMEM;
} else {
return count;
}
}
/* Program memcpy descriptors into the descriptor ring and update s/w head ptr*/
static int mic_dma_prog_memcpy_desc(struct mic_dma_chan *ch, dma_addr_t src,
dma_addr_t dst, size_t len)
{
size_t current_transfer_len;
size_t max_xfer_size = to_mic_dma_dev(ch)->max_xfer_size;
/* 3 is added to make sure we have enough space for status desc */
int num_desc = len / max_xfer_size + 3;
int ret;
if (len % max_xfer_size)
num_desc++;
ret = mic_dma_avail_desc_ring_space(ch, num_desc);
if (ret < 0)
return ret;
do {
current_transfer_len = min(len, max_xfer_size);
mic_dma_memcpy_desc(&ch->desc_ring[ch->head],
src, dst, current_transfer_len);
mic_dma_hw_ring_inc_head(ch);
len -= current_transfer_len;
dst = dst + current_transfer_len;
src = src + current_transfer_len;
} while (len > 0);
return 0;
}
/* It's a h/w quirk and h/w needs 2 status descriptors for every status desc */
static void mic_dma_prog_intr(struct mic_dma_chan *ch)
{
mic_dma_prep_status_desc(&ch->desc_ring[ch->head], 0,
ch->status_dest_micpa, false);
mic_dma_hw_ring_inc_head(ch);
mic_dma_prep_status_desc(&ch->desc_ring[ch->head], 0,
ch->status_dest_micpa, true);
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