/*
* intel_mid_dma.c - Intel Langwell DMA Drivers
*
* Copyright (C) 2008-10 Intel Corp
* Author: Vinod Koul <vinod.koul@intel.com>
* The driver design is based on dw_dmac driver
* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
*
* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
*
*
*/
#include <linux/pci.h>
#include <linux/interrupt.h>
#include <linux/intel_mid_dma.h>
#define MAX_CHAN 4 /*max ch across controllers*/
#include "intel_mid_dma_regs.h"
#define INTEL_MID_DMAC1_ID 0x0814
#define INTEL_MID_DMAC2_ID 0x0813
#define INTEL_MID_GP_DMAC2_ID 0x0827
#define INTEL_MFLD_DMAC1_ID 0x0830
#define LNW_PERIPHRAL_MASK_BASE 0xFFAE8008
#define LNW_PERIPHRAL_MASK_SIZE 0x10
#define LNW_PERIPHRAL_STATUS 0x0
#define LNW_PERIPHRAL_MASK 0x8
struct intel_mid_dma_probe_info {
u8 max_chan;
u8 ch_base;
u16 block_size;
u32 pimr_mask;
};
#define INFO(_max_chan, _ch_base, _block_size, _pimr_mask) \
((kernel_ulong_t)&(struct intel_mid_dma_probe_info) { \
.max_chan = (_max_chan), \
.ch_base = (_ch_base), \
.block_size = (_block_size), \
.pimr_mask = (_pimr_mask), \
})
/*****************************************************************************
Utility Functions*/
/**
* get_ch_index - convert status to channel
* @status: status mask
* @base: dma ch base value
*
* Modify the status mask and return the channel index needing
* attention (or -1 if neither)
*/
static int get_ch_index(int *status, unsigned int base)
{
int i;
for (i = 0; i < MAX_CHAN; i++) {
if (*status & (1 << (i + base))) {
*status = *status & ~(1 << (i + base));
pr_debug("MDMA: index %d New status %x\n", i, *status);
return i;
}
}
return -1;
}
/**
* get_block_ts - calculates dma transaction length
* @len: dma transfer length
* @tx_width: dma transfer src width
* @block_size: dma controller max block size
*
* Based on src width calculate the DMA trsaction length in data items
* return data items or FFFF if exceeds max length for block
*/
static int get_block_ts(int len, int tx_width, int block_size)
{
int byte_width = 0, block_ts = 0;
switch (tx_width) {
case LNW_DMA_WIDTH_8BIT:
byte_width = 1;
break;
case LNW_DMA_WIDTH_16BIT:
byte_width = 2;
break;
case LNW_DMA_WIDTH_32BIT:
default:
byte_width = 4;
break;
}
block_ts = len/byte_width;
if (block_ts > block_size)
block_ts = 0xFFFF;
return block_ts;
}
/*****************************************************************************
DMAC1 interrupt Functions*/
/**
* dmac1_mask_periphral_intr - mask the periphral interrupt
* @midc: dma channel for which masking is required
*
* Masks the DMA periphral interrupt
* this is valid for DMAC1 family controllers only
* This controller should have periphral mask registers already mapped
*/
static void dmac1_mask_periphral_intr(struct intel_mid_dma_chan *midc)
{
u32 pimr;
struct middma_device *mid = to_middma_device(midc->chan.device);
if (mid->pimr_mask) {
pimr = readl(mid->mask_reg + LNW_PERIPHRAL_MASK);
pimr |= mid->pimr_mask;
writel(pimr, mid->mask_reg + LNW_PERIPHRAL_MASK);
}
return;
}
/**
* dmac1_unmask_periphral_intr - unmask the periphral interrupt
* @midc: dma channel for which masking is required
*
* UnMasks the DMA periphral interrupt,
* this is valid for DMAC1 family controllers only
* This controller should have periphral mask registers already mapped
*/
static void dmac1_unmask_periphral_intr(struct intel_mid_dma_chan *midc)
{
u32 pimr;
struct middma_device *mid = to_middma_device(midc->chan.device);
if (mid->pimr_mask) {
pimr = readl(mid->mask_reg + LNW_PERIPHRAL_MASK);
pimr &= ~mid->pimr_mask;
writel(pimr, mid->mask_reg + LNW_PERIPHRAL_MASK);
}
return;
}
/**
* enable_dma_interrupt - enable the periphral interrupt
* @midc: dma channel for which enable interrupt is required
*
* Enable the DMA periphral interrupt,
* this is valid for DMAC1 family controllers only
* This controller should have