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/*
* drivers/dma/imx-dma.c
*
* This file contains a driver for the Freescale i.MX DMA engine
* found on i.MX1/21/27
*
* Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
* Copyright 2012 Javier Martin, Vista Silicon <javier.martin@vista-silicon.com>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/types.h>
#include <linux/mm.h>
#include <linux/interrupt.h>
#include <linux/spinlock.h>
#include <linux/device.h>
#include <linux/dma-mapping.h>
#include <linux/slab.h>
#include <linux/platform_device.h>
#include <linux/dmaengine.h>
#include <linux/module.h>
#include <asm/irq.h>
#include <mach/dma-v1.h>
#include <mach/hardware.h>
#include "dmaengine.h"
#define IMXDMA_MAX_CHAN_DESCRIPTORS 16
enum imxdma_prep_type {
IMXDMA_DESC_MEMCPY,
IMXDMA_DESC_INTERLEAVED,
IMXDMA_DESC_SLAVE_SG,
IMXDMA_DESC_CYCLIC,
};
struct imxdma_desc {
struct list_head node;
struct dma_async_tx_descriptor desc;
enum dma_status status;
dma_addr_t src;
dma_addr_t dest;
size_t len;
unsigned int dmamode;
enum imxdma_prep_type type;
/* For memcpy and interleaved */
unsigned int config_port;
unsigned int config_mem;
/* For interleaved transfers */
unsigned int x;
unsigned int y;
unsigned int w;
/* For slave sg and cyclic */
struct scatterlist *sg;
unsigned int sgcount;
};
struct imxdma_channel {
struct imxdma_engine *imxdma;
unsigned int channel;
unsigned int imxdma_channel;
struct tasklet_struct dma_tasklet;
struct list_head ld_free;
struct list_head ld_queue;
struct list_head ld_active;
int descs_allocated;
enum dma_slave_buswidth word_size;
dma_addr_t per_address;
u32 watermark_level;
struct dma_chan chan;
spinlock_t lock;
struct dma_async_tx_descriptor desc;
enum dma_status status;
int dma_request;
struct scatterlist *sg_list;
};
#define MAX_DMA_CHANNELS 8
struct imxdma_engine {
struct device *dev;
struct device_dma_parameters dma_parms;
struct dma_device dma_device;
struct imxdma_channel channel[MAX_DMA_CHANNELS];
};
static struct imxdma_channel *to_imxdma_chan(struct dma_chan *chan)
{
return container_of(chan, struct imxdma_channel, chan);
}
static inline bool imxdma_chan_is_doing_cyclic(struct imxdma_channel *imxdmac)
{
struct imxdma_desc *desc;
if (!list_empty(&imxdmac->ld_active)) {
desc = list_first_entry(&imxdmac->ld_active, struct imxdma_desc,
node);
if (desc->type == IMXDMA_DESC_CYCLIC)
return true;
}
return false;
}
static void imxdma_irq_handler(int channel, void *data)
{
struct imxdma_channel *imxdmac = data;
tasklet_schedule(&imxdmac->dma_tasklet);
}
static void imxdma_err_handler(int channel, void *data, int error)
{
struct imxdma_channel *imxdmac = data;
tasklet_schedule(&imxdmac->dma_tasklet);
}
static void imxdma_progression(int channel, void *data,
struct scatterlist *sg)
{
struct imxdma_channel *imxdmac = data;
tasklet_schedule(&imxdmac->dma_tasklet);
}
static int imxdma_xfer_desc(struct imxdma_desc *d)
{
struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
int ret;
/* Configure and enable */
switch (d->type) {
case IMXDMA_DESC_MEMCPY:
ret = imx_dma_config_channel(imxdmac->imxdma_channel,
d->config_port, d->config_mem, 0, 0);
if (ret < 0)
return ret;
ret = imx_dma_setup_single(imxdmac->imxdma_channel, d->src,
d->len, d->dest, d->dmamode);
if (ret < 0)
return ret;
break;
case IMXDMA_DESC_CYCLIC:
ret = imx_dma_setup_progression_handler(imxdmac->imxdma_channel,
imxdma_progression);
if (ret < 0)
return ret;
/*
* We fall through here since cyclic transfer is the same as
* slave_sg adding a progression handler and a specific sg
* configuration which is done in 'imxdma_prep_dma_cyclic'.
*/
case IMXDMA_DESC_SLAVE_SG:
if (d->dmamode == DMA_MODE_READ)
ret = imx_dma_setup_sg(imxdmac->imxdma_channel, d->sg,
d->sgcount, d->len, d->src, d->dmamode);
else
ret = imx_dma_setup_sg(imxdmac->imxdma_channel, d->sg,
d->sgcount, d->len, d->dest, d->dmamode);
if (ret < 0)
return ret;
break;
default:
return -EINVAL;
}
imx_dma_enable(imxdmac->imxdma_channel);
return 0;
}
static void imxdma_tasklet(unsigned long data)
{
struct imxdma_channel *imxdmac = (void *)data;
struct imxdma_engine *imxdma = imxdmac->imxdma;
struct imxdma_desc *desc;
spin_lock(&imxdmac->lock);
if (list_empty(&imxdmac->ld_active)) {
/* Someone might have called terminate all */
goto out;
}
desc = list_first_entry(&imxdmac->ld_active, struct imxdma_desc, node);
if (desc->desc.callback)
desc->desc.callback(desc->desc.callback_param);
dma_cookie_complete(&desc->desc);
/* If we are dealing with a cyclic descriptor keep it on ld_active */
if (imxdma_chan_is_doing_cyclic(imxdmac))
goto out;
list_move_tail(imxdmac->ld_active.next, &imxdmac->ld_free);
if (!list_empty(&imxdmac->ld_queue)) {
desc = list_first_entry(&imxdmac->ld_queue, struct imxdma_desc,
node);
list_move_tail(imxdmac->ld_queue.next, &imxdmac->ld_active);
if (imxdma_xfer_desc(desc) < 0)
dev_warn(imxdma->dev, "%s: channel: %d couldn't xfer desc\n",
__func__, imxdmac->channel);
}
out:
spin_unlock(&imxdmac->lock);
}
static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
unsigned long arg)
{
struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
struct dma_slave_config *dmaengine_cfg = (void *)arg;
int ret;
unsigned long flags;
unsigned int mode = 0;
switch (cmd) {
case DMA_TERMINATE_ALL:
|