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/*
* Copyright (C) 2013, Lars-Peter Clausen <lars@metafoo.de>
* JZ4740 DMAC support
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*
*/
#include <linux/dmaengine.h>
#include <linux/dma-mapping.h>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/list.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/irq.h>
#include <linux/clk.h>
#include <asm/mach-jz4740/dma.h>
#include "virt-dma.h"
#define JZ_DMA_NR_CHANS 6
#define JZ_REG_DMA_SRC_ADDR(x) (0x00 + (x) * 0x20)
#define JZ_REG_DMA_DST_ADDR(x) (0x04 + (x) * 0x20)
#define JZ_REG_DMA_TRANSFER_COUNT(x) (0x08 + (x) * 0x20)
#define JZ_REG_DMA_REQ_TYPE(x) (0x0C + (x) * 0x20)
#define JZ_REG_DMA_STATUS_CTRL(x) (0x10 + (x) * 0x20)
#define JZ_REG_DMA_CMD(x) (0x14 + (x) * 0x20)
#define JZ_REG_DMA_DESC_ADDR(x) (0x18 + (x) * 0x20)
#define JZ_REG_DMA_CTRL 0x300
#define JZ_REG_DMA_IRQ 0x304
#define JZ_REG_DMA_DOORBELL 0x308
#define JZ_REG_DMA_DOORBELL_SET 0x30C
#define JZ_DMA_STATUS_CTRL_NO_DESC BIT(31)
#define JZ_DMA_STATUS_CTRL_DESC_INV BIT(6)
#define JZ_DMA_STATUS_CTRL_ADDR_ERR BIT(4)
#define JZ_DMA_STATUS_CTRL_TRANSFER_DONE BIT(3)
#define JZ_DMA_STATUS_CTRL_HALT BIT(2)
#define JZ_DMA_STATUS_CTRL_COUNT_TERMINATE BIT(1)
#define JZ_DMA_STATUS_CTRL_ENABLE BIT(0)
#define JZ_DMA_CMD_SRC_INC BIT(23)
#define JZ_DMA_CMD_DST_INC BIT(22)
#define JZ_DMA_CMD_RDIL_MASK (0xf << 16)
#define JZ_DMA_CMD_SRC_WIDTH_MASK (0x3 << 14)
#define JZ_DMA_CMD_DST_WIDTH_MASK (0x3 << 12)
#define JZ_DMA_CMD_INTERVAL_LENGTH_MASK (0x7 << 8)
#define JZ_DMA_CMD_BLOCK_MODE BIT(7)
#define JZ_DMA_CMD_DESC_VALID BIT(4)
#define JZ_DMA_CMD_DESC_VALID_MODE BIT(3)
#define JZ_DMA_CMD_VALID_IRQ_ENABLE BIT(2)
#define JZ_DMA_CMD_TRANSFER_IRQ_ENABLE BIT(1)
#define JZ_DMA_CMD_LINK_ENABLE BIT(0)
#define JZ_DMA_CMD_FLAGS_OFFSET 22
#define JZ_DMA_CMD_RDIL_OFFSET 16
#define JZ_DMA_CMD_SRC_WIDTH_OFFSET 14
#define JZ_DMA_CMD_DST_WIDTH_OFFSET 12
#define JZ_DMA_CMD_TRANSFER_SIZE_OFFSET 8
#define JZ_DMA_CMD_MODE_OFFSET 7
#define JZ_DMA_CTRL_PRIORITY_MASK (0x3 << 8)
#define JZ_DMA_CTRL_HALT BIT(3)
#define JZ_DMA_CTRL_ADDRESS_ERROR BIT(2)
#define JZ_DMA_CTRL_ENABLE BIT(0)
enum jz4740_dma_width {
JZ4740_DMA_WIDTH_32BIT = 0,
JZ4740_DMA_WIDTH_8BIT = 1,
JZ4740_DMA_WIDTH_16BIT = 2,
};
enum jz4740_dma_transfer_size {
JZ4740_DMA_TRANSFER_SIZE_4BYTE = 0,
JZ4740_DMA_TRANSFER_SIZE_1BYTE = 1,
JZ4740_DMA_TRANSFER_SIZE_2BYTE = 2,
JZ4740_DMA_TRANSFER_SIZE_16BYTE = 3,
JZ4740_DMA_TRANSFER_SIZE_32BYTE = 4,
};
enum jz4740_dma_flags {
JZ4740_DMA_SRC_AUTOINC = 0x2,
JZ4740_DMA_DST_AUTOINC = 0x1,
};
enum jz4740_dma_mode {
JZ4740_DMA_MODE_SINGLE = 0,
JZ4740_DMA_MODE_BLOCK = 1,
};
struct jz4740_dma_sg {
dma_addr_t addr;
unsigned int len;
};
struct jz4740_dma_desc {
struct virt_dma_desc vdesc;
enum dma_transfer_direction direction;
bool cyclic;
unsigned int num_sgs;
struct jz4740_dma_sg sg[];
};
struct jz4740_dmaengine_chan {
struct virt_dma_chan vchan;
unsigned int id;
dma_addr_t fifo_addr;
unsigned int transfer_shift;
struct jz4740_dma_desc *desc;
unsigned int next_sg;
};
struct jz4740_dma_dev {
struct dma_device ddev;
void __iomem *base;
struct clk *clk;
struct jz4740_dmaengine_chan chan[JZ_DMA_NR_CHANS];
};
static struct jz4740_dma_dev *jz4740_dma_chan_get_dev(
struct jz4740_dmaengine_chan *chan)
{
return container_of(chan->vchan.chan.device, struct jz4740_dma_dev,
ddev);
}
static struct jz4740_dmaengine_chan *to_jz4740_dma_chan(struct dma_chan *c)
{
return container_of(c, struct jz4740_dmaengine_chan, vchan.chan);
}
static struct jz4740_dma_desc *to_jz4740_dma_desc(struct virt_dma_desc *vdesc)
{
return container_of(vdesc, struct jz4740_dma_desc, vdesc);
}
static inline uint32_t jz4740_dma_read(struct jz4740_dma_dev *dmadev,
unsigned int reg)
{
return readl(dmadev->base + reg);
}
static inline void jz4740_dma_write(struct jz4740_dma_dev *dmadev,
unsigned reg, uint32_t val)
{
writel(val, dmadev->base + reg);
}
static inline void jz4740_dma_write_mask(struct jz4740_dma_dev *dmadev,
unsigned int reg, uint32_t val, uint32_t mask)
{
uint32_t tmp;
tmp = jz4740_dma_read(dmadev, reg);
tmp &= ~mask;
tmp |= val;
jz4740_dma_write(dmadev, reg, tmp);
}
static struct jz4740_dma_desc *jz4740_dma_alloc_desc(unsigned int num_sgs)
{
return kzalloc(sizeof(struct jz4740_dma_desc) +
sizeof(struct jz4740_dma_sg) * num_sgs, GFP_ATOMIC);
}
static enum jz4740_dma_width jz4740_dma_width(enum dma_slave_buswidth width)
{
switch (width) {
case DMA_SLAVE_BUSWIDTH_1_BYTE:
return JZ4740_DMA_WIDTH_8BIT;
case DMA_SLAVE_BUSWIDTH_2_BYTES:
return JZ4740_DMA_WIDTH_16BIT;
case DMA_SLAVE_BUSWIDTH_4_BYTES:
return JZ4740_DMA_WIDTH_32BIT;
default:
return JZ4740_DMA_WIDTH_32BIT;
}
}
static enum jz4740_dma_transfer_size jz4740_dma_maxburst(u32 maxburst)
{
if (maxburst <= 1)
return JZ4740_DMA_TRANSFER_SIZE_1BYTE;
else if (maxburst <= 3)
return JZ4740_DMA_TRANSFER_SIZE_2BYTE;
else if (maxburst <= 15)
return JZ4740_DMA_TRANSFER_SIZE_4BYTE;
else if (maxburst <= 31)
return JZ4740_DMA_TRANSFER_SIZE_16BYTE;
return JZ4740_DMA_TRANSFER_SIZE_32BYTE;
}
static int jz4740_dma_slave_config(struct dma_chan *c,
struct dma_slave_config *config)
{
struct jz4740_dmaengine_chan *chan = to_jz4740_dma_chan(c);
struct jz4740_dma_dev *dmadev = jz4740_dma_chan_get_dev(chan);
enum jz4740_dma_width src_width;
enum jz4740_dma_width dst_width;
enum jz4740_dma_transfer_size transfer_size;
enum jz4740_dma_flags flags;
uint32_t cmd;
switch (config->direction) {
case DMA_MEM_TO_DEV:
flags = JZ4740_DMA_SRC_AUTOINC;
transfer_size = jz4740_dma_maxburst(config->dst_maxburst);
chan->fifo_addr = config->dst_addr;
break;
case DMA_DEV_TO_MEM:
flags = JZ4740_DMA_DST_AUTOINC;
transfer_size = jz4740_dma_maxburst(config->src_maxburst);
chan->fifo_addr = config->src_addr;
break;
default:
return -EINVAL;
}
src_width = jz4740_dma_width(config->src_addr_width);
dst_width = jz4740_dma_width(config->dst_addr_width);
switch (transfer_size) {
case JZ4740_DMA_TRANSFER_SIZE_2BYTE:
chan->transfer_shift = 1;
break;
case JZ4740_DMA_TRANSFER_SIZE_4BYTE:
chan->transfer_shift = 2;
break;
case JZ4740_DMA_TRANSFER_SIZE_16BYTE:
chan->transfer_shift = 4;
break;
case JZ4740_DMA_TRANSFER_SIZE_32BYTE:
chan->transfer_shift = 5;
break;
default:
chan->transfer_shift = 0;
break;
}
cmd = flags << JZ_DMA_CMD_FLAGS_OFFSET;
cmd |= src_width << JZ_DMA_CMD_SRC_WIDTH_OFFSET;
cmd |= dst_width << JZ_DMA_CMD_DST_WIDTH_OFFSET;
cmd |= transfer_size << JZ_DMA_CMD_TRANSFER_SIZE_OFFSET;
cmd |= JZ4740_DMA_MODE_SINGLE << JZ_DMA_CMD_MODE_OFFSET;
cmd |= JZ_DMA_CMD_TRANSFER_IRQ_ENABLE;
jz4740_dma_write(dmadev, JZ_REG_DMA_CMD(chan->id), cmd);
jz4740_dma_write(dmadev, JZ_REG_DMA_STATUS_CTRL(chan->id), 0);
jz4740_dma_write(dmadev, JZ_REG_DMA_REQ_TYPE(chan->id),
config->slave_id);
return 0;
}
static int jz4740_dma_terminate_all(struct dma_chan *c)
{
struct jz4740_dmaengine_chan *chan = to_jz4740_dma_chan(c
|