// SPDX-License-Identifier: GPL-2.0-only
/*
* DRA7 Clock init
*
* Copyright (C) 2013 Texas Instruments, Inc.
*
* Tero Kristo (t-kristo@ti.com)
*/
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/clk.h>
#include <linux/clkdev.h>
#include <linux/clk/ti.h>
#include <dt-bindings/clock/dra7.h>
#include "clock.h"
#define DRA7_DPLL_GMAC_DEFFREQ 1000000000
#define DRA7_DPLL_USB_DEFFREQ 960000000
static const struct omap_clkctrl_reg_data dra7_mpu_clkctrl_regs[] __initconst = {
{ DRA7_MPU_MPU_CLKCTRL, NULL, 0, "dpll_mpu_m2_ck" },
{ 0 },
};
static const struct omap_clkctrl_reg_data dra7_dsp1_clkctrl_regs[] __initconst = {
{ DRA7_DSP1_MMU0_DSP1_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_dsp_m2_ck" },
{ 0 },
};
static const char * const dra7_ipu1_gfclk_mux_parents[] __initconst = {
"dpll_abe_m2x2_ck",
"dpll_core_h22x2_ck",
NULL,
};
static const struct omap_clkctrl_bit_data dra7_mmu_ipu1_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, dra7_ipu1_gfclk_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_reg_data dra7_ipu1_clkctrl_regs[] __initconst = {
{ DRA7_IPU1_MMU_IPU1_CLKCTRL, dra7_mmu_ipu1_bit_data, CLKF_HW_SUP, "ipu1-clkctrl:0000:24" },
{ 0 },
};
static const char * const dra7_mcasp1_aux_gfclk_mux_parents[] __initconst = {
"per_abe_x1_gfclk2_div",
"video1_clk2_div",
"video2_clk2_div",
"hdmi_clk2_div",
NULL,
};
static const char * const dra7_mcasp1_ahclkx_mux_parents[] __initconst = {
"abe_24m_fclk",
"abe_sys_clk_div",
"func_24m_clk",
"atl_clkin3_ck",
"atl_clkin2_ck",
"atl_clkin1_ck",
"atl_clkin0_ck",
"sys_clkin2",
"ref_clkin0_ck",
"ref_clkin1_ck",
"ref_clkin2_ck",
"ref_clkin3_ck",
"mlb_clk",
"mlbp_clk",
NULL,
};
static const struct omap_clkctrl_bit_data dra7_mcasp1_bit_data[] __initconst = {
{ 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
{ 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
{ 28, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
{ 0 },
};
static const char * const dra7_timer5_gfclk_mux_parents[] __initconst = {
"timer_sys_clk_div",
"sys_32k_ck",
"sys_clkin2",
"ref_clkin0_ck",
"ref_clkin1_ck",
"ref_clkin2_ck",
"ref_clkin3_ck",
"abe_giclk_div",
"video1_div_clk",
"video2_div_clk",
"hdmi_div_clk",
"clkoutmux0_clk_mux",
NULL,
};
static const struct omap_clkctrl_bit_data dra7_timer5_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_timer6_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_timer7_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_bit_data dra7_timer8_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
{ 0 },
};
static const char * const dra7_uart6_gfclk_mux_parents[] __initconst = {
"func_48m_fclk",
"dpll_per_m2x2_ck",
NULL,
};
static const struct omap_clkctrl_bit_data dra7_uart6_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
{ 0 },
};
static const struct omap_clkctrl_reg_data dra7_ipu_clkctrl_regs[] __initconst = {
{ DRA7_IPU_MCASP1_CLKCTRL, dra7_mcasp1_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0000:22" },
{ DRA7_IPU_TIMER5_CLKCTRL, dra7_timer5_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0008:24" },
{ DRA7_IPU_TIMER6_CLKCTRL, dra7_timer6_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0010:24" },
{ DRA7_IPU_TIMER7_CLKCTRL, dra7_timer7_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0018:24" },
{ DRA7_IPU_TIMER8_CLKCTRL, dra7_timer8_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0020:24" },
{ DRA7_IPU_I2C5_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
{ DRA7_IPU_UART6_CLKCTRL, dra7_uart6_bit_data, CLKF_SW_SUP, "ipu-clkctrl:0030:24" },
{ 0 },
};
static const struct omap_clkctrl_reg_data dra7_dsp2_clkctrl_regs[] __initconst = {
{ DRA7_DSP2_MMU0_DSP2_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_dsp_m2_ck" },
{ 0 },
};
static const struct omap_clkctrl_reg_data dra7_rtc_clkctrl_regs[] __initconst = {
{ DRA7_RTC_RTCSS_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
{ 0 },
};
static const struct omap_clkctrl_reg_data dra7_coreaon_clkctrl_regs[] __initconst = {
{ DRA7_COREAON_SMARTREFLEX_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "wkupaon_iclk_mux" },
{ DRA7_COREAON_SMARTREFLEX_CORE_CLKCTRL, NULL, CLKF_SW_SUP,