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/*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/clk.h>
#include <linux/clkdev.h>
#include <linux/clk-provider.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/math64.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/string.h>
#define ADPLL_PLLSS_MMR_LOCK_OFFSET 0x00 /* Managed by MPPULL */
#define ADPLL_PLLSS_MMR_LOCK_ENABLED 0x1f125B64
#define ADPLL_PLLSS_MMR_UNLOCK_MAGIC 0x1eda4c3d
#define ADPLL_PWRCTRL_OFFSET 0x00
#define ADPLL_PWRCTRL_PONIN 5
#define ADPLL_PWRCTRL_PGOODIN 4
#define ADPLL_PWRCTRL_RET 3
#define ADPLL_PWRCTRL_ISORET 2
#define ADPLL_PWRCTRL_ISOSCAN 1
#define ADPLL_PWRCTRL_OFFMODE 0
#define ADPLL_CLKCTRL_OFFSET 0x04
#define ADPLL_CLKCTRL_CLKDCOLDOEN 29
#define ADPLL_CLKCTRL_IDLE 23
#define ADPLL_CLKCTRL_CLKOUTEN 20
#define ADPLL_CLKINPHIFSEL_ADPLL_S 19 /* REVISIT: which bit? */
#define ADPLL_CLKCTRL_CLKOUTLDOEN_ADPLL_LJ 19
#define ADPLL_CLKCTRL_ULOWCLKEN 18
#define ADPLL_CLKCTRL_CLKDCOLDOPWDNZ 17
#define ADPLL_CLKCTRL_M2PWDNZ 16
#define ADPLL_CLKCTRL_M3PWDNZ_ADPLL_S 15
#define ADPLL_CLKCTRL_LOWCURRSTDBY_ADPLL_S 13
#define ADPLL_CLKCTRL_LPMODE_ADPLL_S 12
#define ADPLL_CLKCTRL_REGM4XEN_ADPLL_S 10
#define ADPLL_CLKCTRL_SELFREQDCO_ADPLL_LJ 10
#define ADPLL_CLKCTRL_TINITZ 0
#define ADPLL_TENABLE_OFFSET 0x08
#define ADPLL_TENABLEDIV_OFFSET 0x8c
#define ADPLL_M2NDIV_OFFSET 0x10
#define ADPLL_M2NDIV_M2 16
#define ADPLL_M2NDIV_M2_ADPLL_S_WIDTH 5
#define ADPLL_M2NDIV_M2_ADPLL_LJ_WIDTH 7
#define ADPLL_MN2DIV_OFFSET 0x14
#define ADPLL_MN2DIV_N2 16
#define ADPLL_FRACDIV_OFFSET 0x18
#define ADPLL_FRACDIV_REGSD 24
#define ADPLL_FRACDIV_FRACTIONALM 0
#define ADPLL_FRACDIV_FRACTIONALM_MASK 0x3ffff
#define ADPLL_BWCTRL_OFFSET 0x1c
#define ADPLL_BWCTRL_BWCONTROL 1
#define ADPLL_BWCTRL_BW_INCR_DECRZ 0
#define ADPLL_RESERVED_OFFSET 0x20
#define ADPLL_STATUS_OFFSET 0x24
#define ADPLL_STATUS_PONOUT 31
#define ADPLL_STATUS_PGOODOUT 30
#define ADPLL_STATUS_LDOPWDN 29
#define ADPLL_STATUS_RECAL_BSTATUS3 28
#define ADPLL_STATUS_RECAL_OPPIN 27
#define ADPLL_STATUS_PHASELOCK 10
#define ADPLL_STATUS_FREQLOCK 9
#define ADPLL_STATUS_BYPASSACK 8
#define ADPLL_STATUS_LOSSREF 6
#define ADPLL_STATUS_CLKOUTENACK 5
#define ADPLL_STATUS_LOCK2 4
#define ADPLL_STATUS_M2CHANGEACK 3
#define ADPLL_STATUS_HIGHJITTER 1
#define ADPLL_STATUS_BYPASS 0
#define ADPLL_STATUS_PREPARED_MASK (BIT(ADPLL_STATUS_PHASELOCK) | \
BIT(ADPLL_STATUS_FREQLOCK))
#define ADPLL_M3DIV_OFFSET 0x28 /* Only on MPUPLL */
#define ADPLL_M3DIV_M3 0
#define ADPLL_M3DIV_M3_WIDTH 5
#define ADPLL_M3DIV_M3_MASK 0x1f
#define ADPLL_RAMPCTRL_OFFSET 0x2c /* Only on MPUPLL */
#define ADPLL_RAMPCTRL_CLKRAMPLEVEL 19
#define ADPLL_RAMPCTRL_CLKRAMPRATE 16
#define ADPLL_RAMPCTRL_RELOCK_RAMP_EN 0
#define MAX_ADPLL_INPUTS 3
#define MAX_ADPLL_OUTPUTS 4
#define ADPLL_MAX_RETRIES 5
#define to_dco(_hw) container_of(_hw, struct ti_adpll_dco_data, hw)
#define to_adpll(_hw) container_of(_hw, struct ti_adpll_data, dco)
#define to_clkout(_hw) container_of(_hw, struct ti_adpll_clkout_data, hw)
enum ti_adpll_clocks {
TI_ADPLL_DCO,
TI_ADPLL_DCO_GATE,
TI_ADPLL_N2,
TI_ADPLL_M2,
TI_ADPLL_M2_GATE,
TI_ADPLL_BYPASS,
TI_ADPLL_HIF,
TI_ADPLL_DIV2,
TI_ADPLL_CLKOUT,
TI_ADPLL_CLKOUT2,
TI_ADPLL_M3,
};
#define TI_ADPLL_NR_CLOCKS (TI_ADPLL_M3 + 1)
enum ti_adpll_inputs {
TI_ADPLL_CLKINP,
TI_ADPLL_CLKINPULOW,
TI_ADPLL_CLKINPHIF,
};
enum ti_adpll_s_outputs {
TI_ADPLL_S_DCOCLKLDO,
TI_ADPLL_S_CLKOUT,
TI_ADPLL_S_CLKOUTX2,
TI_ADPLL_S_CLKOUTHIF,
};
enum ti_adpll_lj_outputs {
TI_ADPLL_LJ_CLKDCOLDO,
TI_ADPLL_LJ_CLKOUT,
TI_ADPLL_LJ_CLKOUTLDO,
};
struct ti_adpll_platform_data {
const bool is_type_s;
const int nr_max_inputs;
const int nr_max_outputs;
const int output_index;
};
struct ti_adpll_clock {
struct clk *clk;
struct clk_lookup *cl;
void (*unregister)(struct clk *clk);
};
struct ti_adpll_dco_data {
struct clk_hw hw;
};
struct ti_adpll_clkout_data {
struct ti_adpll_data *adpll;
struct clk_gate gate;
struct clk_hw hw;
};
struct ti_adpll_data {
struct device *dev;
const struct ti_adpll_platform_data *c;
struct device_node *np;
unsigned long pa;
void __iomem *iobase;
void __iomem *regs;
spinlock_t lock; /* For ADPLL shared register access */
const char *parent_names[MAX_ADPLL_INPUTS];
struct clk *parent_clocks[MAX_ADPLL_INPUTS];
struct ti_adpll_clock *clocks;
struct clk_onecell_data outputs;
struct ti_adpll_dco_data dco;
};
static const char *ti_adpll_clk_get_name(struct ti_adpll_data *d,
int output_index,
const char *postfix)
{
const char *name;
int err;
if (output_index >= 0) {
err = of_property_read_string_index(d->np,
"clock-output-names",
output_index,
&name);
if (err)
return NULL;
} else {
const char *base_name = "adpll";
char *buf;
buf = devm_kzalloc(d->dev, 8 + 1 + strlen(base_name) + 1 +
strlen(postfix), GFP_KERNEL);
if (!buf)
return NULL;
sprintf(buf, "%08lx.%s.%s", d->pa, base_name, postfix);
name = buf;
}
return name;
}
#define ADPLL_MAX_CON_ID 16 /* See MAX_CON_ID */
static int ti_adpll_setup_clock(struct ti_adpll_data *d, struct clk *clock,
int index, int output_index, const char *name,
void (*unregister)(struct clk *clk))
{
struct clk_lookup *cl;
const char *postfix = NULL;
char con_id[ADPLL_MAX_CON_ID];
d->clocks[index].clk = clock;
d->clocks[index].unregister = unregister;
/* Separate con_id in format "pll040dcoclkldo" to fit MAX_CON_ID */
postfix = strrchr(name, '.');
if (postfix && strlen(postfix) > 1
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