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|
/*
* drivers/clk/tegra/clk-emc.c
*
* Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
*
* Author:
* Mikko Perttunen <mperttunen@nvidia.com>
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/clk-provider.h>
#include <linux/clk.h>
#include <linux/clkdev.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/sort.h>
#include <linux/string.h>
#include <soc/tegra/fuse.h>
#include <soc/tegra/emc.h>
#include "clk.h"
#define CLK_SOURCE_EMC 0x19c
#define CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR_SHIFT 0
#define CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR_MASK 0xff
#define CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR(x) (((x) & CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR_MASK) << \
CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR_SHIFT)
#define CLK_SOURCE_EMC_EMC_2X_CLK_SRC_SHIFT 29
#define CLK_SOURCE_EMC_EMC_2X_CLK_SRC_MASK 0x7
#define CLK_SOURCE_EMC_EMC_2X_CLK_SRC(x) (((x) & CLK_SOURCE_EMC_EMC_2X_CLK_SRC_MASK) << \
CLK_SOURCE_EMC_EMC_2X_CLK_SRC_SHIFT)
static const char * const emc_parent_clk_names[] = {
"pll_m", "pll_c", "pll_p", "clk_m", "pll_m_ud",
"pll_c2", "pll_c3", "pll_c_ud"
};
/*
* List of clock sources for various parents the EMC clock can have.
* When we change the timing to a timing with a parent that has the same
* clock source as the current parent, we must first change to a backup
* timing that has a different clock source.
*/
#define EMC_SRC_PLL_M 0
#define EMC_SRC_PLL_C 1
#define EMC_SRC_PLL_P 2
#define EMC_SRC_CLK_M 3
#define EMC_SRC_PLL_C2 4
#define EMC_SRC_PLL_C3 5
static const char emc_parent_clk_sources[] = {
EMC_SRC_PLL_M, EMC_SRC_PLL_C, EMC_SRC_PLL_P, EMC_SRC_CLK_M,
EMC_SRC_PLL_M, EMC_SRC_PLL_C2, EMC_SRC_PLL_C3, EMC_SRC_PLL_C
};
struct emc_timing {
unsigned long rate, parent_rate;
u8 parent_index;
struct clk *parent;
u32 ram_code;
};
struct tegra_clk_emc {
struct clk_hw hw;
void __iomem *clk_regs;
struct clk *prev_parent;
bool changing_timing;
struct device_node *emc_node;
struct tegra_emc *emc;
int num_timings;
struct emc_timing *timings;
spinlock_t *lock;
};
/* Common clock framework callback implementations */
static unsigned long emc_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct tegra_clk_emc *tegra;
u32 val, div;
tegra = container_of(hw, struct tegra_clk_emc, hw);
/*
* CCF wrongly assumes that the parent won't change during set_rate,
* so get the parent rate explicitly.
*/
parent_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
val = readl(tegra->clk_regs + CLK_SOURCE_EMC);
div = val & CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR_MASK;
return parent_rate / (div + 2) * 2;
}
/*
* Rounds up unless no higher rate exists, in which case down. This way is
* safer since things have EMC rate floors. Also don't touch parent_rate
* since we don't want the CCF to play with our parent clocks.
*/
static int emc_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
{
struct tegra_clk_emc *tegra;
u8 ram_code = tegra_read_ram_code();
struct emc_timing *timing = NULL;
int i;
tegra = container_of(hw, struct tegra_clk_emc, hw);
for (i = 0; i < tegra->num_timings; i++) {
if (tegra->timings[i].ram_code != ram_code)
continue;
timing = tegra->timings + i;
if (timing->rate > req->max_rate) {
i = min(i, 1);
req->rate = tegra->timings[i - 1].rate;
return 0;
}
if (timing->rate < req->min_rate)
continue;
if (timing->rate >= req->rate) {
req->rate = timing->rate;
return 0;
}
}
if (timing) {
req->rate = timing->rate;
return 0;
}
req->rate = clk_hw_get_rate(hw);
return 0;
}
static u8 emc_get_parent(struct clk_hw *hw)
{
struct tegra_clk_emc *tegra;
u32 val;
tegra = container_of(hw, struct tegra_clk_emc, hw);
val = readl(tegra->clk_regs + CLK_SOURCE_EMC);
return (val >> CLK_SOURCE_EMC_EMC_2X_CLK_SRC_SHIFT)
& CLK_SOURCE_EMC_EMC_2X_CLK_SRC_MASK;
}
static struct tegra_emc *emc_ensure_emc_driver(struct tegra_clk_emc *tegra)
{
struct platform_device *pdev;
if (tegra->emc)
return tegra->emc;
if (!tegra->emc_node)
return NULL;
pdev = of_find_device_by_node(tegra->emc_node);
if (!pdev) {
pr_err("%s: could not get external memory controller\n",
__func__);
return NULL;
}
of_node_put(tegra->emc_node);
tegra->emc_node = NULL;
tegra->emc = platform_get_drvdata(pdev);
if (!tegra->emc) {
pr_err("%s: cannot find EMC driver\n", __func__);
return NULL;
}
return tegra->emc;
}
static int emc_set_timing(struct tegra_clk_emc *tegra,
struct emc_timing *timing)
{
int err;
u8 div;
u32 car_value;
unsigned long flags = 0;
struct tegra_emc *emc = emc_ensure_emc_driver(tegra);
if (!emc)
return -ENOENT;
pr_debug("going to rate %ld prate %ld p %s\n", timing->rate,
timing->parent_rate, __clk_get_name(timing->parent));
if (emc_get_parent(&tegra->hw) == timing->parent_index &&
clk_get_rate(timing->parent) != timing->parent_rate) {
BUG();
return -EINVAL;
}
tegra->changing_timing = true;
err = clk_set_rate(timing->parent, timing->parent_rate);
if (err) {
pr_err("cannot change parent %s rate to %ld: %d\n",
__clk_get_name(timing->parent), timing->parent_rate,
err);
return err;
}
err = clk_prepare_enable(timing->parent);
if (err) {
pr_err("cannot enable parent clock: %d\n", err);
return err;
}
div = timing->parent_rate / (timing->rate / 2) - 2;
err = tegra_emc_prepare_timing_change(emc, timing->rate);
if (err)
return err;
spin_lock_irqsave(tegra->lock, flags);
car_value = readl(tegra->clk_regs + CLK_SOURCE_EMC);
car_value &= ~CLK_SOURCE_EMC_EMC_2X_CLK_SRC(~0);
car_value |= CLK_SOURCE_EMC_EMC_2X_CLK_SRC(timing->parent_index);
car_value &= ~CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR(~0);
car_value |= CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR(div);
writel(car_value, tegra->clk_regs + CLK_SOURCE_EMC);
spin_unlock_irqrestore(tegra->lock, flags);
tegra_emc_complete_timing_change(emc, timing->rate);
clk_hw_reparent(&tegra->hw, __clk_get_hw(timing->parent));
clk_disable_unprepare(tegra->prev_parent);
tegra->prev_parent = timing->parent;
tegra->changing_timing = false;
return 0;
}
/*
* Get backup timing to use as an intermediate step when a change between
* two timings with the same clock source has been requested. First try to
* find a timing with a higher clock rate to avoid a rate below any set rate
* floors. If that is not possible, find a lower rate.
*/
static struct emc_timing *get_backup_timing(struct tegra_clk_emc
|