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/*
* SPEAr3xx machines clock framework source file
*
* Copyright (C) 2012 ST Microelectronics
* Viresh Kumar <viresh.kumar@st.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/clk.h>
#include <linux/clkdev.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/of_platform.h>
#include <linux/spinlock_types.h>
#include <mach/misc_regs.h>
#include "clk.h"
static DEFINE_SPINLOCK(_lock);
#define PLL1_CTR (MISC_BASE + 0x008)
#define PLL1_FRQ (MISC_BASE + 0x00C)
#define PLL2_CTR (MISC_BASE + 0x014)
#define PLL2_FRQ (MISC_BASE + 0x018)
#define PLL_CLK_CFG (MISC_BASE + 0x020)
/* PLL_CLK_CFG register masks */
#define MCTR_CLK_SHIFT 28
#define MCTR_CLK_MASK 3
#define CORE_CLK_CFG (MISC_BASE + 0x024)
/* CORE CLK CFG register masks */
#define GEN_SYNTH2_3_CLK_SHIFT 18
#define GEN_SYNTH2_3_CLK_MASK 1
#define HCLK_RATIO_SHIFT 10
#define HCLK_RATIO_MASK 2
#define PCLK_RATIO_SHIFT 8
#define PCLK_RATIO_MASK 2
#define PERIP_CLK_CFG (MISC_BASE + 0x028)
/* PERIP_CLK_CFG register masks */
#define UART_CLK_SHIFT 4
#define UART_CLK_MASK 1
#define FIRDA_CLK_SHIFT 5
#define FIRDA_CLK_MASK 2
#define GPT0_CLK_SHIFT 8
#define GPT1_CLK_SHIFT 11
#define GPT2_CLK_SHIFT 12
#define GPT_CLK_MASK 1
#define PERIP1_CLK_ENB (MISC_BASE + 0x02C)
/* PERIP1_CLK_ENB register masks */
#define UART_CLK_ENB 3
#define SSP_CLK_ENB 5
#define I2C_CLK_ENB 7
#define JPEG_CLK_ENB 8
#define FIRDA_CLK_ENB 10
#define GPT1_CLK_ENB 11
#define GPT2_CLK_ENB 12
#define ADC_CLK_ENB 15
#define RTC_CLK_ENB 17
#define GPIO_CLK_ENB 18
#define DMA_CLK_ENB 19
#define SMI_CLK_ENB 21
#define GMAC_CLK_ENB 23
#define USBD_CLK_ENB 24
#define USBH_CLK_ENB 25
#define C3_CLK_ENB 31
#define RAS_CLK_ENB (MISC_BASE + 0x034)
#define RAS_AHB_CLK_ENB 0
#define RAS_PLL1_CLK_ENB 1
#define RAS_APB_CLK_ENB 2
#define RAS_32K_CLK_ENB 3
#define RAS_24M_CLK_ENB 4
#define RAS_48M_CLK_ENB 5
#define RAS_PLL2_CLK_ENB 7
#define RAS_SYNT0_CLK_ENB 8
#define RAS_SYNT1_CLK_ENB 9
#define RAS_SYNT2_CLK_ENB 10
#define RAS_SYNT3_CLK_ENB 11
#define PRSC0_CLK_CFG (MISC_BASE + 0x044)
#define PRSC1_CLK_CFG (MISC_BASE + 0x048)
#define PRSC2_CLK_CFG (MISC_BASE + 0x04C)
#define AMEM_CLK_CFG (MISC_BASE + 0x050)
#define AMEM_CLK_ENB 0
#define CLCD_CLK_SYNT (MISC_BASE + 0x05C)
#define FIRDA_CLK_SYNT (MISC_BASE + 0x060)
#define UART_CLK_SYNT (MISC_BASE + 0x064)
#define GMAC_CLK_SYNT (MISC_BASE + 0x068)
#define GEN0_CLK_SYNT (MISC_BASE + 0x06C)
#define GEN1_CLK_SYNT (MISC_BASE + 0x070)
#define GEN2_CLK_SYNT (MISC_BASE + 0x074)
#define GEN3_CLK_SYNT (MISC_BASE + 0x078)
/* pll rate configuration table, in ascending order of rates */
static struct pll_rate_tbl pll_rtbl[] = {
{.mode = 0, .m = 0x53, .n = 0x0C, .p = 0x1}, /* vco 332 & pll 166 MHz */
{.mode = 0, .m = 0x85, .n = 0x0C, .p = 0x1}, /* vco 532 & pll 266 MHz */
{.mode = 0, .m = 0xA6, .n = 0x0C, .p = 0x1}, /* vco 664 & pll 332 MHz */
};
/* aux rate configuration table, in ascending order of rates */
static struct aux_rate_tbl aux_rtbl[] = {
/* For PLL1 = 332 MHz */
{.xscale = 2, .yscale = 27, .eq = 0}, /* 12.296 MHz */
{.xscale = 2, .yscale = 8, .eq = 0}, /* 41.5 MHz */
{.xscale = 2, .yscale = 4, .eq = 0}, /* 83 MHz */
{.xscale = 1, .yscale = 2, .eq = 1}, /* 166 MHz */
};
/* gpt rate configuration table, in ascending order of rates */
static struct gpt_rate_tbl gpt_rtbl[] = {
/* For pll1 = 332 MHz */
{.mscale = 4, .nscale = 0}, /* 41.5 MHz */
{.mscale = 2, .nscale = 0}, /* 55.3 MHz */
{.mscale = 1, .nscale = 0}, /* 83 MHz */
};
/* clock parents */
static const char *uart0_parents[] = { "pll3_48m_clk", "uart_synth_gate_clk", };
static const char *firda_parents[] = { "pll3_48m_clk", "firda_synth_gate_clk",
};
static const char *gpt0_parents[] = { "pll3_48m_clk", "gpt0_synth_clk", };
static const char *gpt1_parents[] = { "pll3_48m_clk", "gpt1_synth_clk", };
static const char *gpt2_parents[] = { "pll3_48m_clk", "gpt2_synth_clk", };
static const char *gen2_3_parents[] = { "pll1_clk", "pll2_clk", };
static const char *ddr_parents[] = { "ahb_clk", "ahbmult2_clk", "none",
"pll2_clk", };
#ifdef CONFIG_MACH_SPEAR300
static void __init spear300_clk_init(void)
{
struct clk *clk;
clk = clk_register_fixed_factor(NULL, "clcd_clk", "ras_pll3_48m_clk", 0,
1, 1);
clk_register_clkdev(clk, NULL, "60000000.clcd");
clk = clk_register_fixed_factor(NULL, "fsmc_clk", "ras_ahb_clk", 0, 1,
1);
clk_register_clkdev(clk, NULL, "94000000.flash");
clk = clk_register_fixed_factor(NULL, "sdhci_clk", "ras_ahb_clk", 0, 1,
1);
clk_register_clkdev(clk, NULL, "70000000.sdhci");
clk = clk_register_fixed_factor(NULL, "gpio1_clk", "ras_apb_clk", 0, 1,
1);
clk_register_clkdev(clk, NULL, "a9000000.gpio");
clk = clk_register_fixed_factor(NULL, "kbd_clk", "ras_apb_clk", 0, 1,
1);
clk_register_clkdev(clk, NULL, "a0000000.kbd");
}
#endif
/* array of all spear 310 clock lookups */
#ifdef CONFIG_MACH_SPEAR310
static void __init spear310_clk_init(void)
{
struct clk *clk;
clk = clk_register_fixed_factor(NULL, "emi_clk", "ras_ahb_clk", 0, 1,
1);
clk_register_clkdev(clk, "emi", NULL);
clk = clk_register_fixed_factor(NULL, "fsmc_clk", "ras_ahb_clk", 0, 1,
1);
clk_register_clkdev(clk, NULL, "44000000.flash");
clk = clk_register_fixed_factor(NULL, "tdm_clk", "ras_ahb_clk", 0, 1,
1);
clk_register_clkdev(clk, NULL, "tdm");
clk = clk_register_fixed_factor(NULL, "uart1_clk", "ras_apb_clk", 0, 1,
1);
clk_register_clkdev(clk, NULL, "b2000000.serial");
clk = clk_register_fixed_factor(NULL, "uart2_clk", "ras_apb_clk", 0, 1,
1);
clk_register_clkdev(clk, NULL, "b2080000.serial");
clk = clk_register_fixed_factor(NULL, "uart3_clk", "ras_apb_clk", 0, 1,
1);
clk_register_clkdev(clk, NULL, "b2100000.serial");
clk = clk_register_fixed_factor(NULL, "uart4_clk", "ras_apb_clk", 0, 1,
1);
clk_register_clkdev(clk, NULL, "b2180000.serial");
clk = clk_register_fixed_factor(NULL, "uart5_clk", "ras_apb_clk", 0, 1,
1);
clk_register_clkdev(clk, NULL, "b2200000.serial");
}
#endif
/* array of all spear 320 clock lookups */
#ifdef CONFIG_MACH_SPEAR320
#define SMII_PCLK_SHIFT 18
#define SMII_PCLK_MASK 2
#define SMII_PCLK_VAL_PAD 0x0
#define SMII_PCLK_VAL_PLL2 0x1
#define SMII_PCLK_VAL_SYNTH0 0x2
#define SDHCI_PCLK_SHIFT 15
#define SDHCI_PCLK_MASK 1
#define SDHCI_PCLK_VAL_48M 0x0
#define SDHCI_PCLK_VAL_SYNTH3 0x1
#define I2S_REF_PCLK_SHIFT 8
#define I2S_REF_PCLK_MASK 1
#define I2S_REF_PCLK_SYNTH_VAL 0x1
#define I2S_REF_PCLK_PLL2_VAL 0x0
#define UART1_PCLK_SHIFT 6
#define UART1_PCLK_MASK 1
#define SPEAR320_UARTX_PCLK_VAL_SYNTH1 0x0
#define SPEAR320_UARTX_PCLK_VAL_APB 0x1
static const char *i2s_ref_parents[] = { "ras_pll2_clk",
"ras_gen2_synth_gate_clk", };
static const char *sdhci_parents[] = { "ras_pll3_48m_clk",
"ras_gen3_synth_gate_clk",
};
static const char *smii0_parents[] = { "smii_125m_pad", "ras_pll2_clk",
"ras_gen0_syn
|