1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
|
/*
* Copyright (c) 2014 MediaTek Inc.
* Author: James Liao <jamesjj.liao@mediatek.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/clkdev.h>
#include <linux/delay.h>
#include "clk-mtk.h"
#define REG_CON0 0
#define REG_CON1 4
#define CON0_BASE_EN BIT(0)
#define CON0_PWR_ON BIT(0)
#define CON0_ISO_EN BIT(1)
#define CON0_PCW_CHG BIT(31)
#define AUDPLL_TUNER_EN BIT(31)
#define POSTDIV_MASK 0x7
#define INTEGER_BITS 7
/*
* MediaTek PLLs are configured through their pcw value. The pcw value describes
* a divider in the PLL feedback loop which consists of 7 bits for the integer
* part and the remaining bits (if present) for the fractional part. Also they
* have a 3 bit power-of-two post divider.
*/
struct mtk_clk_pll {
struct clk_hw hw;
void __iomem *base_addr;
void __iomem *pd_addr;
void __iomem *pwr_addr;
void __iomem *tuner_addr;
void __iomem *pcw_addr;
const struct mtk_pll_data *data;
};
static inline struct mtk_clk_pll *to_mtk_clk_pll(struct clk_hw *hw)
{
return container_of(hw, struct mtk_clk_pll, hw);
}
static int mtk_pll_is_prepared(struct clk_hw *hw)
{
struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
return (readl(pll->base_addr + REG_CON0) & CON0_BASE_EN) != 0;
}
static unsigned long __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin,
u32 pcw, int postdiv)
{
int pcwbits = pll->data->pcwbits;
int pcwfbits;
u64 vco;
u8 c = 0;
/* The fractional part of the PLL divider. */
pcwfbits = pcwbits > INTEGER_BITS ? pcwbits - INTEGER_BITS : 0;
vco = (u64)fin * pcw;
if (pcwfbits && (vco & GENMASK(pcwfbits - 1, 0)))
c = 1;
vco >>= pcwfbits;
if (c)
vco++;
return ((unsigned long)vco + postdiv - 1) / postdiv;
}
static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw,
int postdiv)
{
u32 con1, val;
int pll_en;
pll_en = readl(pll->base_addr + REG_CON0) & CON0_BASE_EN;
/* set postdiv */
val = readl(pll->pd_addr);
val &= ~(POSTDIV_MASK << pll->data->pd_shift);
val |= (ffs(postdiv) - 1) << pll->data->pd_shift;
/* postdiv and pcw need to set at the same time if on same register */
if (pll->pd_addr != pll->pcw_addr) {
writel(val, pll->pd_addr);
val = readl(pll->pcw_addr);
}
/* set pcw */
val &= ~GENMASK(pll->data->pcw_shift + pll->data->pcwbits - 1,
pll->data->pcw_shift);
val |= pcw << pll->data->pcw_shift;
writel(val, pll->pcw_addr);
con1 = readl(pll->base_addr + REG_CON1);
if (pll_en)
con1 |= CON0_PCW_CHG;
writel(con1, pll->base_addr + REG_CON1);
if (pll->tuner_addr)
writel(con1 + 1, pll->tuner_addr);
if (pll_en)
udelay(20);
}
/*
* mtk_pll_calc_values - calculate good values for a given input frequency.
* @pll: The pll
* @pcw: The pcw value (output)
* @postdiv: The post divider (output)
* @freq: The desired target frequency
* @fin: The input frequency
*
*/
static void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv,
u32 freq, u32 fin)
{
unsigned long fmin = 1000 * MHZ;
const struct mtk_pll_div_table *div_table = pll->data->div_table;
u64 _pcw;
u32 val;
if (freq > pll->data->fmax)
freq = pll->data->fmax;
if (div_table) {
if (freq > div_table[0].freq)
freq = div_table[0].freq;
for (val = 0; div_table[val + 1].freq != 0; val++) {
if (freq > div_table[val + 1].freq)
break;
}
*postdiv = 1 << val;
} else {
for (val = 0; val < 5; val++) {
*postdiv = 1 << val;
if ((u64)freq * *postdiv >= fmin)
break;
}
}
/* _pcw = freq * postdiv / fin * 2^pcwfbits */
_pcw = ((u64)freq << val) << (pll->data->pcwbits - INTEGER_BITS);
do_div(_pcw, fin);
*pcw = (u32)_pcw;
}
static int mtk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
u32 pcw = 0;
u32 postdiv;
mtk_pll_calc_values(pll, &pcw, &postdiv, rate, parent_rate);
mtk_pll_set_rate_regs(pll, pcw, postdiv);
return 0;
}
static unsigned long mtk_pll_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
u32 postdiv;
u32 pcw;
postdiv = (readl(pll->pd_addr) >> pll->data->pd_shift) & POSTDIV_MASK;
postdiv = 1 << postdiv;
pcw = readl(pll->pcw_addr) >> pll->data->pcw_shift;
pcw &= GENMASK(pll->data->pcwbits - 1, 0);
return __mtk_pll_recalc_rate(pll, parent_rate, pcw, postdiv);
}
static long mtk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *prate)
{
struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
u32 pcw = 0;
int postdiv;
mtk_pll_calc_values(pll, &pcw, &postdiv, rate, *prate);
return __mtk_pll_recalc_rate(pll, *prate, pcw, postdiv);
}
static int mtk_pll_prepare(struct clk_hw *hw)
{
struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
u32 r;
r = readl(pll->pwr_addr) | CON0_PWR_ON;
writel(r, pll->pwr_addr);
udelay(1);
r = readl(pll->pwr_addr) & ~CON0_ISO_EN;
writel(r, pll->pwr_addr);
udelay(1);
r = readl(pll->base_addr + REG_CON0);
r |= pll->data->en_mask;
writel(r, pll->base_addr + REG_CON0);
if (pll->tuner_addr) {
r = readl(pll->tuner_addr) | AUDPLL_TUNER_EN;
writel(r, pll->tuner_addr);
}
udelay(20);
if (pll->data->flags & HAVE_RST_BAR) {
r = readl(pll->base_addr + REG_CON0);
r |= pll->data->rst_bar_mask;
writel(r, pll->base_addr + REG_CON0);
}
return 0;
}
static void mtk_pll_unprepare(struct clk_hw *hw)
{
struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
u32 r;
if (pll->data->flags & HAVE_RST_BAR) {
r = readl(pll->base_addr + REG_CON0);
r &= ~pll->data->rst_bar_mask;
writel(r, pll->base_addr + REG_CON0);
}
if (pll->tuner_addr) {
r = readl(pll->tuner_addr) & ~
|