// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2001-2021, Huawei Tech. Co., Ltd.
* Author: chenjun <chenjun14@huawei.com>
*
* Copyright (c) 2018, Linaro Ltd.
* Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
*/
#include <dt-bindings/clock/hi3670-clock.h>
#include <linux/clk-provider.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include "clk.h"
static const struct hisi_fixed_rate_clock hi3670_fixed_rate_clks[] = {
{ HI3670_CLKIN_SYS, "clkin_sys", NULL, 0, 19200000, },
{ HI3670_CLKIN_REF, "clkin_ref", NULL, 0, 32764, },
{ HI3670_CLK_FLL_SRC, "clk_fll_src", NULL, 0, 134400000, },
{ HI3670_CLK_PPLL0, "clk_ppll0", NULL, 0, 1660000000, },
{ HI3670_CLK_PPLL1, "clk_ppll1", NULL, 0, 1866000000, },
{ HI3670_CLK_PPLL2, "clk_ppll2", NULL, 0, 1920000000, },
{ HI3670_CLK_PPLL3, "clk_ppll3", NULL, 0, 1200000000, },
{ HI3670_CLK_PPLL4, "clk_ppll4", NULL, 0, 900000000, },
{ HI3670_CLK_PPLL6, "clk_ppll6", NULL, 0, 393216000, },
{ HI3670_CLK_PPLL7, "clk_ppll7", NULL, 0, 1008000000, },
{ HI3670_CLK_PPLL_PCIE, "clk_ppll_pcie", NULL, 0, 100000000, },
{ HI3670_CLK_PCIEPLL_REV, "clk_pciepll_rev", NULL, 0, 100000000, },
{ HI3670_CLK_SCPLL, "clk_scpll", NULL, 0, 245760000, },
{ HI3670_PCLK, "pclk", NULL, 0, 20000000, },
{ HI3670_CLK_UART0_DBG, "clk_uart0_dbg", NULL, 0, 19200000, },
{ HI3670_CLK_UART6, "clk_uart6", NULL, 0, 19200000, },
{ HI3670_OSC32K, "osc32k", NULL, 0, 32764, },
{ HI3670_OSC19M, "osc19m", NULL, 0, 19200000, },
{ HI3670_CLK_480M, "clk_480m", NULL, 0, 480000000, },
{ HI3670_CLK_INVALID, "clk_invalid", NULL, 0, 10000000, },
};
/* crgctrl */
static const struct hisi_fixed_factor_clock hi3670_crg_fixed_factor_clks[] = {
{ HI3670_CLK_DIV_SYSBUS, "clk_div_sysbus", "clk_mux_sysbus",
1, 7, 0, },
{ HI3670_CLK_FACTOR_MMC, "clk_factor_mmc", "clkin_sys",
1, 6, 0, },
{ HI3670_CLK_SD_SYS, "clk_sd_sys", "clk_sd_sys_gt",
1, 6, 0, },
{ HI3670_CLK_SDIO_SYS, "clk_sdio_sys", "clk_sdio_sys_gt",
1, 6, 0, },
{ HI3670_CLK_DIV_A53HPM, "clk_div_a53hpm", "clk_a53hpm_andgt",
1, 4, 0, },
{ HI3670_CLK_DIV_320M, "clk_div_320m", "clk_320m_pll_gt",
1, 5, 0, },
{ HI3670_PCLK_GATE_UART0, "pclk_gate_uart0", "clk_mux_uartl",
1, 1, 0, },
{ HI3670_CLK_FACTOR_UART0, "clk_factor_uart0", "clk_mux_uart0",
1, 1, 0, },
{ HI3670_CLK_FACTOR_USB3PHY_PLL, "clk_factor_usb3phy_pll", "clk_ppll0",
1, 60, 0, },
{ HI3670_CLK_GATE_ABB_USB, "clk_gate_abb_usb", "clk_gate_usb_tcxo_en",
1, 1, 0, },
{ HI3670_CLK_GATE_UFSPHY_REF, "clk_gate_ufsphy_ref", "clkin_sys",
1, 1, 0, },
{ HI3670_ICS_VOLT_HIGH, "ics_volt_high", "peri_volt_hold",
1, 1, 0, },
{ HI3670_ICS_VOLT_MIDDLE, "ics_volt_middle", "peri_volt_middle",
1, 1, 0, },
{ HI3670_VENC_VOLT_HOLD, "venc_volt_hold", "peri_volt_hold",
1, 1, 0, },
{ HI3670_VDEC_VOLT_HOLD, "vdec_volt_hold", "peri_volt_hold",
1, 1, 0, },
{ HI3670_EDC_VOLT_HOLD, "edc_volt_hold", "peri_volt_hold",
1, 1, 0, },
{ HI3670_CLK_ISP_SNCLK_FAC, "clk_isp_snclk_fac", "clk_isp_snclk_angt",
1, 10, 0