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/*
* U300 clock implementation
* Copyright (C) 2007-2012 ST-Ericsson AB
* License terms: GNU General Public License (GPL) version 2
* Author: Linus Walleij <linus.walleij@stericsson.com>
* Author: Jonas Aaberg <jonas.aberg@stericsson.com>
*/
#include <linux/clk.h>
#include <linux/clkdev.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/clk-provider.h>
#include <linux/spinlock.h>
#include <linux/of.h>
/* APP side SYSCON registers */
/* CLK Control Register 16bit (R/W) */
#define U300_SYSCON_CCR (0x0000)
#define U300_SYSCON_CCR_I2S1_USE_VCXO (0x0040)
#define U300_SYSCON_CCR_I2S0_USE_VCXO (0x0020)
#define U300_SYSCON_CCR_TURN_VCXO_ON (0x0008)
#define U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK (0x0007)
#define U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER (0x04)
#define U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW (0x03)
#define U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE (0x02)
#define U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH (0x01)
#define U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST (0x00)
/* CLK Status Register 16bit (R/W) */
#define U300_SYSCON_CSR (0x0004)
#define U300_SYSCON_CSR_PLL208_LOCK_IND (0x0002)
#define U300_SYSCON_CSR_PLL13_LOCK_IND (0x0001)
/* Reset lines for SLOW devices 16bit (R/W) */
#define U300_SYSCON_RSR (0x0014)
#define U300_SYSCON_RSR_PPM_RESET_EN (0x0200)
#define U300_SYSCON_RSR_ACC_TMR_RESET_EN (0x0100)
#define U300_SYSCON_RSR_APP_TMR_RESET_EN (0x0080)
#define U300_SYSCON_RSR_RTC_RESET_EN (0x0040)
#define U300_SYSCON_RSR_KEYPAD_RESET_EN (0x0020)
#define U300_SYSCON_RSR_GPIO_RESET_EN (0x0010)
#define U300_SYSCON_RSR_EH_RESET_EN (0x0008)
#define U300_SYSCON_RSR_BTR_RESET_EN (0x0004)
#define U300_SYSCON_RSR_UART_RESET_EN (0x0002)
#define U300_SYSCON_RSR_SLOW_BRIDGE_RESET_EN (0x0001)
/* Reset lines for FAST devices 16bit (R/W) */
#define U300_SYSCON_RFR (0x0018)
#define U300_SYSCON_RFR_UART1_RESET_ENABLE (0x0080)
#define U300_SYSCON_RFR_SPI_RESET_ENABLE (0x0040)
#define U300_SYSCON_RFR_MMC_RESET_ENABLE (0x0020)
#define U300_SYSCON_RFR_PCM_I2S1_RESET_ENABLE (0x0010)
#define U300_SYSCON_RFR_PCM_I2S0_RESET_ENABLE (0x0008)
#define U300_SYSCON_RFR_I2C1_RESET_ENABLE (0x0004)
#define U300_SYSCON_RFR_I2C0_RESET_ENABLE (0x0002)
#define U300_SYSCON_RFR_FAST_BRIDGE_RESET_ENABLE (0x0001)
/* Reset lines for the rest of the peripherals 16bit (R/W) */
#define U300_SYSCON_RRR (0x001c)
#define U300_SYSCON_RRR_CDS_RESET_EN (0x4000)
#define U300_SYSCON_RRR_ISP_RESET_EN (0x2000)
#define U300_SYSCON_RRR_INTCON_RESET_EN (0x1000)
#define U300_SYSCON_RRR_MSPRO_RESET_EN (0x0800)
#define U300_SYSCON_RRR_XGAM_RESET_EN (0x0100)
#define U300_SYSCON_RRR_XGAM_VC_SYNC_RESET_EN (0x0080)
#define U300_SYSCON_RRR_NANDIF_RESET_EN (0x0040)
#define U300_SYSCON_RRR_EMIF_RESET_EN (0x0020)
#define U300_SYSCON_RRR_DMAC_RESET_EN (0x0010)
#define U300_SYSCON_RRR_CPU_RESET_EN (0x0008)
#define U300_SYSCON_RRR_APEX_RESET_EN (0x0004)
#define U300_SYSCON_RRR_AHB_RESET_EN (0x0002)
#define U300_SYSCON_RRR_AAIF_RESET_EN (0x0001)
/* Clock enable for SLOW peripherals 16bit (R/W) */
#define U300_SYSCON_CESR (0x0020)
#define U300_SYSCON_CESR_PPM_CLK_EN (0x0200)
#define U300_SYSCON_CESR_ACC_TMR_CLK_EN (0x0100)
#define U300_SYSCON_CESR_APP_TMR_CLK_EN (0x0080)
#define U300_SYSCON_CESR_KEYPAD_CLK_EN (0x0040)
#define U300_SYSCON_CESR_GPIO_CLK_EN (0x0010)
#define U300_SYSCON_CESR_EH_CLK_EN (0x0008)
#define U300_SYSCON_CESR_BTR_CLK_EN (0x0004)
#define U300_SYSCON_CESR_UART_CLK_EN (0x0002)
#define U300_SYSCON_CESR_SLOW_BRIDGE_CLK_EN (0x0001)
/* Clock enable for FAST peripherals 16bit (R/W) */
#define U300_SYSCON_CEFR (0x0024)
#define U300_SYSCON_CEFR_UART1_CLK_EN (0x0200)
#define U300_SYSCON_CEFR_I2S1_CORE_CLK_EN (0x0100)
#define U300_SYSCON_CEFR_I2S0_CORE_CLK_EN (0x0080)
#define U300_SYSCON_CEFR_SPI_CLK_EN (0x0040)
#define U300_SYSCON_CEFR_MMC_CLK_EN (0x0020)
#define U300_SYSCON_CEFR_I2S1_CLK_EN (0x0010)
#define U300_SYSCON_CEFR_I2S0_CLK_EN (0x0008)
#define U300_SYSCON_CEFR_I2C1_CLK_EN (0x0004)
#define U300_SYSCON_CEFR_I2C0_CLK_EN (0x0002)
#define U300_SYSCON_CEFR_FAST_BRIDGE_CLK_EN (0x0001)
/* Clock enable for the rest of the peripherals 16bit (R/W) */
#define U300_SYSCON_CERR (0x0028)
#define U300_SYSCON_CERR_CDS_CLK_EN (0x2000)
#define U300_SYSCON_CERR_ISP_CLK_EN (0x1000)
#define U300_SYSCON_CERR_MSPRO_CLK_EN (0x0800)
#define U300_SYSCON_CERR_AHB_SUBSYS_BRIDGE_CLK_EN (0x0400)
#define U300_SYSCON_CERR_SEMI_CLK_EN (0x0200)
#define U300_SYSCON_CERR_XGAM_CLK_EN (0x0100)
#define U300_SYSCON_CERR_VIDEO_ENC_CLK_EN (0x0080)
#define U300_SYSCON_CERR_NANDIF_CLK_EN (0x0040)
#define U300_SYSCON_CERR_EMIF_CLK_EN (0x0020)
#define U300_SYSCON_CERR_DMAC_CLK_EN (0x0010)
#define U300_SYSCON_CERR_CPU_CLK_EN (0x0008)
#define U300_SYSCON_CERR_APEX_CLK_EN (0x0004)
#define U300_SYSCON_CERR_AHB_CLK_EN (0x0002)
#define U300_SYSCON_CERR_AAIF_CLK_EN (0x0001)
/* Single block clock enable 16bit (-/W) */
#define U300_SYSCON_SBCER (0x002c)
#define U300_SYSCON_SBCER_PPM_CLK_EN (0x0009)
#define U300_SYSCON_SBCER_ACC_TMR_CLK_EN (0x0008)
#define U300_SYSCON_SBCER_APP_TMR_CLK_EN (0x0007)
#define U300_SYSCON_SBCER_KEYPAD_CLK_EN (0x0006)
#define U300_SYSCON_SBCER_GPIO_CLK_EN (0x0004)
#define U300_SYSCON_SBCER_EH_CLK_EN (0x0003)
#define U300_SYSCON_SBCER_BTR_CLK_EN (0x0002)
#define U300_SYSCON_SBCER_UART_CLK_EN (0x0001)
#define U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN (0x0000)
#define U300_SYSCON_SBCER_UART1_CLK_EN (0x0019)
#define U300_SYSCON_SBCER_I2S1_CORE_CLK_EN (0x0018)
#define U300_SYSCON_SBCER_I2S0_CORE_CLK_EN (0x0017)
#define U300_SYSCON_SBCER_SPI_CLK_EN (0x0016)
#define U300_SYSCON_SBCER_MMC_CLK_EN (0x0015)
#define U300_SYSCON_SBCER_I2S1_CLK_EN (0x0014)
#define U300_SYSCON_SBCER_I2S0_CLK_EN (0x0013)
#define U300_SYSCON_SBCER_I2C1_CLK_EN (0x0012)
#define U300_SYSCON_SBCER_I2C0_CLK_EN (0x0011)
#define U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN (0x0010)
#define U300_SYSCON_SBCER_CDS_CLK_EN (0x002D)
#define U300_SYSCON_SBCER_ISP_CLK_EN (0x002C)
#define U300_SYSCON_SBCER_MSPRO_CLK_EN (0x002B)
#define U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN (0x002A)
#define U300_SYSCON_SBCER_SEMI_CLK_EN (0x0029)
#define U300_SYSCON_SBCER_XGAM_CLK_EN (0x0028)
#define U300_SYSCON_SBCER_VIDEO_ENC_CLK_EN (0x0027)
#define U300_SYSCON_SBCER_NANDIF_CLK_EN (0x0026)
#define U300_SYSCON_SBCER_EMIF_CLK_EN (0x0025)
#define U300_SYSCON_SBCER_DMAC_CLK_EN (0x0024)
#define U300_SYSCON_SBCER_CPU_CLK_EN (0x0023)
#define U300_SYSCON_SBCER_APEX_CLK_EN (0x0022)
#define U300_SYSCON_SBCER_AHB_CLK_EN (0x0021)
#define U300_SYSCON_SBCER_AAIF_CLK_EN (0x0020)
/* Single block clock disable 16bit (-/W) */
#define U300_SYSCON_SBCDR (0x0030)
/* Same values as above for SBCER */
/* Clock force SLOW peripherals 16bit (R/W) */
#define U300_SYSCON_CFSR (0x003c)
#define U300_SYSCON_CFSR_PPM_CLK_FORCE_EN (0x0200)
#define U300_SYSCON_CFSR_ACC_TMR_CLK_FORCE_EN (0x0100)
#define U300_SYSCON_CFSR_APP_TMR_CLK_FORCE_EN (0x0080)
#define U300_SYSCON_CFSR_KEYPAD_CLK_FORCE_EN (0x0020)
#define U300_SYSCON_CFSR_GPIO_CLK_FORCE_EN (0x0010)
#define U300_SYSCON_CFSR_EH_CLK_FORCE_EN (0x0008)
#define U300_SYSCON_CFSR_BTR_CLK_FORCE_EN (0x0004)
#define U300_SYSCON_CFSR_UART_CLK_FORCE_EN (0x0002)
#define U300_SYSCON_CFSR_SLOW_BRIDGE_CLK_FORCE_EN (0x0001)
/* Clock force FAST peripherals 16bit (R/W) */
#define U300_SYSCON_CFFR (0x40)
/* Values not defined. Define if you want to use them. */
/* Clock force the rest of the peripherals 16bit (R/W) */
#define U300_SYSCON_CFRR (0x44)
#define U300_SYSCON_CFRR_CDS_CLK_FORCE_EN (0x2000)
#define U300_SYSCON_CFRR_ISP_CLK_FORCE_EN (0x1000)
#define U300_SYSCON_CFRR_MSPRO_CLK_FORCE_EN (0x0800)
#define U300_SYSCON_CFRR_AHB_SUBSYS_BRIDGE_CLK_FORCE_EN (0x0400)
#define U300_SYSCON_CFRR_SEMI_CLK_FORCE_EN (0x0200)
#define U300_SYSCON_CFRR_XGAM_CLK_FORCE_EN (0x0100)
#define U300_SYSCON_CFRR_VIDEO_ENC_CLK_FORCE_EN (0x0080)
#define U300_SYSCON_CFRR_NANDIF_CLK_FORCE_EN (0x0040)
#define U300_SYSCON_CFRR_EMIF_CLK_FORCE_EN (0x0020)
#define U300_SYSCON_CFRR_DMAC_CLK_FORCE_EN (0x0010)
#define U300_SYSCON_CFRR_CPU_CLK_FORCE_EN (0x0008)
#define U300_SYSCON_CFRR_APEX_CLK_FORCE_EN (0x0004)
#define U300_SYSCON_CFRR_AHB_CLK_FORCE_EN (0x0002)
#define U300_SYSCON_CFRR_AAIF_CLK_FORCE_EN (0x0001)
/* PLL208 Frequency Control 16bit (R/W) */
#define U300_SYSCON_PFCR (0x48)
#define U300_SYSCON_PFCR_DPLL_MULT_NUM (0x000F)
/* Power Management Control 16bit (R/W) */
#define U300_SYSCON_PMCR (0x50)
#define U300_SYSCON_PMCR_DCON_ENABLE (0x0002)
#define U300_SYSCON_PMCR_PWR_MGNT_ENABLE (0x0001)
/* Reset Out 16bit (R/W) */
#define U300_SYSCON_RCR (0x6c)
#define U300_SYSCON_RCR_RESOUT0_RST_N_DISABLE (0x0001)
/* EMIF Slew Rate Control 16bit (R/W) */
#define U300_SYSCON_SRCLR (0x70)
#define U300_SYSCON_SRCLR_MASK (0x03FF)
#define U300_SYSCON_SRCLR_VALUE (0x03FF)
#define U300_SYSCON_SRCLR_EMIF_1_SLRC_5_B (0x0200)
#define U300_SYSCON_SRCLR_EMIF_1_SLRC_5_A (0x0100)
#define U300_SYSCON_SRCLR_EMIF_1_SLRC_4_B (0x0080)
#define U300_SYSCON_SRCLR_EMIF_1_SLRC_4_A (0x0040)
#define U300_SYSCON_SRCLR_EMIF_1_SLRC_3_B (0x0020)
#define U300_SYSCON_SRCLR_EMIF_1_SLRC_3_A (0x0010)
#define U300_SYSCON_SRCLR_EMIF_1_SLRC_2_B (0x0008)
#define U300_SYSCON_SRCLR_EMIF_1_SLRC_2_A (0x0004)
#define U300_SYSCON_SRCLR_EMIF_1_SLRC_1_B (0x0002)
#define U300_SYSCON_SRCLR_EMIF_1_SLRC_1_A (0x0001)
/* EMIF Clock Control Register 16bit (R/W) */
#define U300_SYSCON_ECCR (0x0078)
#define U300_SYSCON_ECCR_MASK (0x000F)
#define U300_SYSCON_ECCR_EMIF_1_STATIC_CLK_EN_N_DISABLE (0x0008)
#define U300_SYSCON_ECCR_EMIF_1_RET_OUT_CLK_EN_N_DISABLE (0x0004)
#define U300_SYSCON_ECCR_EMIF_MEMCLK_RET_EN_N_DISABLE (0x0002)
#define U300_SYSCON_ECCR_EMIF_SDRCLK_RET_EN_N_DISABLE (0x0001)
/* MMC/MSPRO frequency divider register 0 16bit (R/W) */
#define U300_SYSCON_MMF0R (0x90)
#define U300_SYSCON_MMF0R_MASK (0x00FF)
#define U300_SYSCON_MMF0R_FREQ_0_HIGH_MASK (0x00F0)
#define U300_SYSCON_MMF0R_FREQ_0_LOW_MASK (0x000F)
/* MMC/MSPRO frequency divider register 1 16bit (R/W) */
#define U300_SYSCON_MMF1R (0x94)
#define U300_SYSCON_MMF1R_MASK (0x00FF)
#define U300_SYSCON_MMF1R_FREQ_1_HIGH_MASK (0x00F0)
#define U300_SYSCON_MMF1R_FREQ_1_LOW_MASK (0x000F)
/* Clock control for the MMC and MSPRO blocks 16bit (R/W) */
#define U300_SYSCON_MMCR (0x9C)
#define U300_SYSCON_MMCR_MASK (0x0003)
#define U300_SYSCON_MMCR_MMC_FB_CLK_SEL_ENABLE (0x0002)
#define U300_SYSCON_MMCR_MSPRO_FREQSEL_ENABLE (0x0001)
/* SYS_0_CLK_CONTROL first clock control 16bit (R/W) */
#define U300_SYSCON_S0CCR (0x120)
#define U300_SYSCON_S0CCR_FIELD_MASK (0x43FF)
#define U300_SYSCON_S0CCR_CLOCK_REQ (0x4000)
#define U300_SYSCON_S0CCR_CLOCK_REQ_MONITOR (0x2000)
#define U300_SYSCON_S0CCR_CLOCK_INV (0x0200)
#define U300_SYSCON_S0CCR_CLOCK_FREQ_MASK (0x01E0)
#define U300_SYSCON_S0CCR_CLOCK_SELECT_MASK (0x001E)
#define U300_SYSCON_S0CCR_CLOCK_ENABLE (0x0001)
#define U300_SYSCON_S0CCR_SEL_MCLK (0x8<<1)
#define U300_SYSCON_S0CCR_SEL_ACC_FSM_CLK (0xA<<1)
#define U300_SYSCON_S0CCR_SEL_PLL60_48_CLK (0xC<<1)
#define U300_SYSCON_S0CCR_SEL_PLL60_60_CLK (0xD<<1)
#define U300_SYSCON_S0CCR_SEL_ACC_PLL208_CLK (0xE<<1)
#define U300_SYSCON_S0CCR_SEL_APP_PLL13_CLK (0x0<<1)
#define U300_SYSCON_S0CCR_SEL_APP_FSM_CLK (0x2<<1)
#define U300_SYSCON_S0CCR_SEL_RTC_CLK (0x4<<1)
#define U300_SYSCON_S0CCR_SEL_APP_PLL208_CLK (0x6<<1)
/* SYS_1_CLK_CONTROL second clock control 16 bit (R/W) */
#define U300_SYSCON_S1CCR (0x124)
#define U300_SYSCON_S1CCR_FIELD_MASK (0x43FF)
#define U300_SYSCON_S1CCR_CLOCK_REQ (0x4000)
#define U300_SYSCON_S1CCR_CLOCK_REQ_MONITOR (0x2000)
#define U300_SYSCON_S1CCR_CLOCK_INV (0x0200)
#define U300_SYSCON_S1CCR_CLOCK_FREQ_MASK (0x01E0)
#define U300_SYSCON_S1CCR_CLOCK_SELECT_MASK (0x001E)
#define U300_SYSCON_S1CCR_CLOCK_ENABLE (0x0001)
#define U300_SYSCON_S1CCR_SEL_MCLK (0x8<<1)
#define U300_SYSCON_S1CCR_SEL_ACC_FSM_CLK (0xA<<1)
#define U300_SYSCON_S1CCR_SEL_PLL60_48_CLK (0xC<<1)
#define U300_SYSCON_S1CCR_SEL_PLL60_60_CLK (0xD<<1)
#define U300_SYSCON_S1CCR_SEL_ACC_PLL208_CLK (0xE<<1)
#define U300_SYSCON_S1CCR_SEL_ACC_PLL13_CLK (0x0<<1)
#define U300_SYSCON_S1CCR_SEL_APP_FSM_CLK (0x2<<1)
#define U300_SYSCON_S1CCR_SEL_RTC_CLK (0x4<<1)
#define U300_SYSCON_S1CCR_SEL_APP_PLL208_CLK (0x6<<1)
/* SYS_2_CLK_CONTROL third clock contol 16 bit (R/W) */
#define U300_SYSCON_S2CCR (0x128)
#define U300_SYSCON_S2CCR_FIELD_MASK (0xC3FF)
#define U300_SYSCON_S2CCR_CLK_STEAL (0x8000)
#define U300_SYSCON_S2CCR_CLOCK_REQ (0x4000)
#define U300_SYSCON_S2CCR_CLOCK_REQ_MONITOR (0x2000)
#define U300_SYSCON_S2CCR_CLOCK_INV (0x0200)
#define U300_SYSCON_S2CCR_CLOCK_FREQ_MASK (0x01E0)
#define U300_SYSCON_S2CCR_CLOCK_SELECT_MASK (0x001E)
#define U300_SYSCON_S2CCR_CLOCK_ENABLE (0x0001)
#define U300_SYSCON_S2CCR_SEL_MCLK (0x8<<1)
#define U300_SYSCON_S2
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