path: root/drivers/atm/fore200e.h

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _FORE200E_H
#define _FORE200E_H

#ifdef __KERNEL__

/* rx buffer sizes */

#define SMALL_BUFFER_SIZE    384     /* size of small buffers (multiple of 48 (PCA) and 64 (SBA) bytes) */
#define LARGE_BUFFER_SIZE    4032    /* size of large buffers (multiple of 48 (PCA) and 64 (SBA) bytes) */


#define RBD_BLK_SIZE	     32      /* nbr of supplied rx buffers per rbd */


#define MAX_PDU_SIZE	     65535   /* maximum PDU size supported by AALs */


#define BUFFER_S1_SIZE       SMALL_BUFFER_SIZE    /* size of small buffers, scheme 1 */
#define BUFFER_L1_SIZE       LARGE_BUFFER_SIZE    /* size of large buffers, scheme 1 */

#define BUFFER_S2_SIZE       SMALL_BUFFER_SIZE    /* size of small buffers, scheme 2 */
#define BUFFER_L2_SIZE       LARGE_BUFFER_SIZE    /* size of large buffers, scheme 2 */

#define BUFFER_S1_NBR        (RBD_BLK_SIZE * 6)
#define BUFFER_L1_NBR        (RBD_BLK_SIZE * 4)

#define BUFFER_S2_NBR        (RBD_BLK_SIZE * 6)
#define BUFFER_L2_NBR        (RBD_BLK_SIZE * 4)


#define QUEUE_SIZE_CMD       16	     /* command queue capacity       */
#define QUEUE_SIZE_RX	     64	     /* receive queue capacity       */
#define QUEUE_SIZE_TX	     256     /* transmit queue capacity      */
#define QUEUE_SIZE_BS        32	     /* buffer supply queue capacity */

#define FORE200E_VPI_BITS     0
#define FORE200E_VCI_BITS    10
#define NBR_CONNECT          (1 << (FORE200E_VPI_BITS + FORE200E_VCI_BITS)) /* number of connections */


#define TSD_FIXED            2
#define TSD_EXTENSION        0
#define TSD_NBR              (TSD_FIXED + TSD_EXTENSION)


/* the cp starts putting a received PDU into one *small* buffer,
   then it uses a number of *large* buffers for the trailing data. 
   we compute here the total number of receive segment descriptors 
   required to hold the largest possible PDU */

#define RSD_REQUIRED  (((MAX_PDU_SIZE - SMALL_BUFFER_SIZE + LARGE_BUFFER_SIZE) / LARGE_BUFFER_SIZE) + 1)

#define RSD_FIXED     3

/* RSD_REQUIRED receive segment descriptors are enough to describe a max-sized PDU,
   but we have to keep the size of the receive PDU descriptor multiple of 32 bytes,
   so we add one extra RSD to RSD_EXTENSION 
   (WARNING: THIS MAY CHANGE IF BUFFER SIZES ARE MODIFIED) */

#define RSD_EXTENSION  ((RSD_REQUIRED - RSD_FIXED) + 1)
#define RSD_NBR         (RSD_FIXED + RSD_EXTENSION)


#define FORE200E_DEV(d)          ((struct fore200e*)((d)->dev_data))
#define FORE200E_VCC(d)          ((struct fore200e_vcc*)((d)->dev_data))

/* bitfields endian games */

#if defined(__LITTLE_ENDIAN_BITFIELD)
#define BITFIELD2(b1, b2)                    b1; b2;
#define BITFIELD3(b1, b2, b3)                b1; b2; b3;
#define BITFIELD4(b1, b2, b3, b4)            b1; b2; b3; b4;
#define BITFIELD5(b1, b2, b3, b4, b5)        b1; b2; b3; b4; b5;
#define BITFIELD6(b1, b2, b3, b4, b5, b6)    b1; b2; b3; b4; b5; b6;
#elif defined(__BIG_ENDIAN_BITFIELD)
#define BITFIELD2(b1, b2)                                    b2; b1;
#define BITFIELD3(b1, b2, b3)                            b3; b2; b1;
#define BITFIELD4(b1, b2, b3, b4)                    b4; b3; b2; b1;
#define BITFIELD5(b1, b2, b3, b4, b5)            b5; b4; b3; b2; b1;
#define BITFIELD6(b1, b2, b3, b4, b5, b6)    b6; b5; b4; b3; b2; b1;
#else
#error unknown bitfield endianess
#endif

 
/* ATM cell header (minus HEC byte) */

typedef struct atm_header {
    BITFIELD5( 
        u32 clp :  1,    /* cell loss priority         */
        u32 plt :  3,    /* payload type               */
        u32 vci : 16,    /* virtual channel identifier */
        u32 vpi :  8,    /* virtual path identifier    */
        u32 gfc :  4     /* generic flow control       */
   )
} atm_header_t;


/* ATM adaptation layer id */

typedef enum fore200e_aal {
    FORE200E_AAL0  = 0,
    FORE200E_AAL34 = 4,
    FORE200E_AAL5  = 5,
} fore200e_aal_t;


/* transmit PDU descriptor specification */

typedef struct tpd_spec {
    BITFIELD4(
        u32               length : 16,    /* total PDU length            */
        u32               nseg   :  8,    /* number of transmit segments */
        enum fore200e_aal aal    :  4,    /* adaptation layer            */
        u32               intr   :  4     /* interrupt requested         */
    )
} tpd_spec_t;


/* transmit PDU rate control */

typedef struct tpd_rate
{
    BITFIELD2( 
        u32 idle_cells : 16,    /* number of idle cells to insert   */
        u32 data_cells : 16     /* number of data cells to transmit */
    )
} tpd_rate_t;


/* transmit segment descriptor */

typedef struct tsd {
    u32 buffer;    /* transmit buffer DMA address */
    u32 length;    /* number of bytes in buffer   */
} tsd_t;


/* transmit PDU descriptor */

typedef struct tpd {
    struct atm_header atm_header;        /* ATM header minus HEC byte    */
    struct tpd_spec   spec;              /* tpd specification            */
    struct tpd_rate   rate;              /* tpd rate control             */
    u32               pad;               /* reserved                     */
    struct tsd        tsd[ TSD_NBR ];    /* transmit segment descriptors */
} tpd_t;


/* receive segment descriptor */

typedef struct rsd {
    u32 handle;    /* host supplied receive buffer handle */
    u32 length;    /* number of bytes in buffer           */
} rsd_t;


/* receive PDU descriptor */

typedef struct rpd {
    struct atm_header atm_header;        /* ATM header minus HEC byte   */
    u32               nseg;              /* number of receive segments  */
    struct rsd        rsd[ RSD_NBR ];    /* receive segment descriptors */
} rpd_t;


/* buffer scheme */

typedef enum buffer_scheme {
    BUFFER_SCHEME_ONE,
    BUFFER_SCHEME_TWO,
    BUFFER_SCHEME_NBR    /* always last */
} buffer_scheme_t;


/* buffer magnitude */

typedef enum buffer_magn {
    BUFFER_MAGN_SMALL,
    BUFFER_MAGN_LARGE,
    BUFFER_MAGN_NBR    /* always last */
} buffer_magn_t;


/* receive buffer descriptor */

typedef struct rbd {
    u32 handle;          /* host supplied handle            */
    u32 buffer_haddr;    /* host DMA address of host buffer */
} rbd_t;


/* receive buffer descriptor block */

typedef struct rbd_block {
    struct rbd rbd[ RBD_BLK_SIZE ];    /* receive buffer descriptor */
} rbd_block_t;


/* tpd DMA address */

typedef struct tpd_haddr {
    BITFIELD3( 
        u32 size  :  4,    /* tpd size expressed in 32 byte blocks     */
        u32 pad   :  1,    /* reserved                                 */
        u32 haddr : 27     /* tpd DMA addr aligned on 32 byte boundary */
    )
} tpd_haddr_t;

#define TPD_HADDR_SHIFT 5  /* addr aligned on 32 byte boundary */

/* cp resident transmit queue entry */

typedef struct cp_txq_entry {
    struct tpd_haddr tpd_haddr;       /* host DMA address of tpd                */
    u32              status_haddr;    /* host DMA address of completion status  */
} cp_txq_entry_t;


/* cp resident receive queue entry */

typedef struct cp_rxq_entry {
    u32 rpd_haddr;       /* host DMA address of rpd                */
    u32 status_haddr;    /* host DMA address of completion status  */
} cp_rxq_entry_t;


/* cp resident buffer supply queue entry */

typedef struct cp_bsq_entry {
    u32 rbd_block_haddr;    /* host DMA address of rbd block          */
    u32 status_haddr;       /* host DMA address of completion status  */
} cp_bsq_entry_t;


/* completion status */

typedef volatile enum status {
    STATUS_PENDING  = (1<<0),    /* initial status (written by host)  */
    STATUS_COMPLETE = (1<<1),    /* completion status (written by cp) */
    STATUS_FREE     = (1<<2),    /* initial status (written by