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|
/*
* Renesas R-Car SATA driver
*
* Author: Vladimir Barinov <source@cogentembedded.com>
* Copyright (C) 2013-2015 Cogent Embedded, Inc.
* Copyright (C) 2013-2015 Renesas Solutions Corp.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/ata.h>
#include <linux/libata.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/err.h>
#define DRV_NAME "sata_rcar"
/* SH-Navi2G/ATAPI-ATA compatible task registers */
#define DATA_REG 0x100
#define SDEVCON_REG 0x138
/* SH-Navi2G/ATAPI module compatible control registers */
#define ATAPI_CONTROL1_REG 0x180
#define ATAPI_STATUS_REG 0x184
#define ATAPI_INT_ENABLE_REG 0x188
#define ATAPI_DTB_ADR_REG 0x198
#define ATAPI_DMA_START_ADR_REG 0x19C
#define ATAPI_DMA_TRANS_CNT_REG 0x1A0
#define ATAPI_CONTROL2_REG 0x1A4
#define ATAPI_SIG_ST_REG 0x1B0
#define ATAPI_BYTE_SWAP_REG 0x1BC
/* ATAPI control 1 register (ATAPI_CONTROL1) bits */
#define ATAPI_CONTROL1_ISM BIT(16)
#define ATAPI_CONTROL1_DTA32M BIT(11)
#define ATAPI_CONTROL1_RESET BIT(7)
#define ATAPI_CONTROL1_DESE BIT(3)
#define ATAPI_CONTROL1_RW BIT(2)
#define ATAPI_CONTROL1_STOP BIT(1)
#define ATAPI_CONTROL1_START BIT(0)
/* ATAPI status register (ATAPI_STATUS) bits */
#define ATAPI_STATUS_SATAINT BIT(11)
#define ATAPI_STATUS_DNEND BIT(6)
#define ATAPI_STATUS_DEVTRM BIT(5)
#define ATAPI_STATUS_DEVINT BIT(4)
#define ATAPI_STATUS_ERR BIT(2)
#define ATAPI_STATUS_NEND BIT(1)
#define ATAPI_STATUS_ACT BIT(0)
/* Interrupt enable register (ATAPI_INT_ENABLE) bits */
#define ATAPI_INT_ENABLE_SATAINT BIT(11)
#define ATAPI_INT_ENABLE_DNEND BIT(6)
#define ATAPI_INT_ENABLE_DEVTRM BIT(5)
#define ATAPI_INT_ENABLE_DEVINT BIT(4)
#define ATAPI_INT_ENABLE_ERR BIT(2)
#define ATAPI_INT_ENABLE_NEND BIT(1)
#define ATAPI_INT_ENABLE_ACT BIT(0)
/* Access control registers for physical layer control register */
#define SATAPHYADDR_REG 0x200
#define SATAPHYWDATA_REG 0x204
#define SATAPHYACCEN_REG 0x208
#define SATAPHYRESET_REG 0x20C
#define SATAPHYRDATA_REG 0x210
#define SATAPHYACK_REG 0x214
/* Physical layer control address command register (SATAPHYADDR) bits */
#define SATAPHYADDR_PHYRATEMODE BIT(10)
#define SATAPHYADDR_PHYCMD_READ BIT(9)
#define SATAPHYADDR_PHYCMD_WRITE BIT(8)
/* Physical layer control enable register (SATAPHYACCEN) bits */
#define SATAPHYACCEN_PHYLANE BIT(0)
/* Physical layer control reset register (SATAPHYRESET) bits */
#define SATAPHYRESET_PHYRST BIT(1)
#define SATAPHYRESET_PHYSRES BIT(0)
/* Physical layer control acknowledge register (SATAPHYACK) bits */
#define SATAPHYACK_PHYACK BIT(0)
/* Serial-ATA HOST control registers */
#define BISTCONF_REG 0x102C
#define SDATA_REG 0x1100
#define SSDEVCON_REG 0x1204
#define SCRSSTS_REG 0x1400
#define SCRSERR_REG 0x1404
#define SCRSCON_REG 0x1408
#define SCRSACT_REG 0x140C
#define SATAINTSTAT_REG 0x1508
#define SATAINTMASK_REG 0x150C
/* SATA INT status register (SATAINTSTAT) bits */
#define SATAINTSTAT_SERR BIT(3)
#define SATAINTSTAT_ATA BIT(0)
/* SATA INT mask register (SATAINTSTAT) bits */
#define SATAINTMASK_SERRMSK BIT(3)
#define SATAINTMASK_ERRMSK BIT(2)
#define SATAINTMASK_ERRCRTMSK BIT(1)
#define SATAINTMASK_ATAMSK BIT(0)
#define SATA_RCAR_INT_MASK (SATAINTMASK_SERRMSK | \
SATAINTMASK_ATAMSK)
/* Physical Layer Control Registers */
#define SATAPCTLR1_REG 0x43
#define SATAPCTLR2_REG 0x52
#define SATAPCTLR3_REG 0x5A
#define SATAPCTLR4_REG 0x60
/* Descriptor table word 0 bit (when DTA32M = 1) */
#define SATA_RCAR_DTEND BIT(0)
#define SATA_RCAR_DMA_BOUNDARY 0x1FFFFFFEUL
/* Gen2 Physical Layer Control Registers */
#define RCAR_GEN2_PHY_CTL1_REG 0x1704
#define RCAR_GEN2_PHY_CTL1 0x34180002
#define RCAR_GEN2_PHY_CTL1_SS 0xC180 /* Spread Spectrum */
#define RCAR_GEN2_PHY_CTL2_REG 0x170C
#define RCAR_GEN2_PHY_CTL2 0x00002303
#define RCAR_GEN2_PHY_CTL3_REG 0x171C
#define RCAR_GEN2_PHY_CTL3 0x000B0194
#define RCAR_GEN2_PHY_CTL4_REG 0x1724
#define RCAR_GEN2_PHY_CTL4 0x00030994
#define RCAR_GEN2_PHY_CTL5_REG 0x1740
#define RCAR_GEN2_PHY_CTL5 0x03004001
#define RCAR_GEN2_PHY_CTL5_DC BIT(1) /* DC connection */
#define RCAR_GEN2_PHY_CTL5_TR BIT(2) /* Termination Resistor */
enum sata_rcar_type {
RCAR_GEN1_SATA,
RCAR_GEN2_SATA,
RCAR_R8A7790_ES1_SATA,
};
struct sata_rcar_priv {
void __iomem *base;
struct clk *clk;
enum sata_rcar_type type;
};
static void sata_rcar_gen1_phy_preinit(struct sata_rcar_priv *priv)
{
void __iomem *base = priv->base;
/* idle state */
iowrite32(0, base + SATAPHYADDR_REG);
/* reset */
iowrite32(SATAPHYRESET_PHYRST, base + SATAPHYRESET_REG);
udelay(10);
/* deassert reset */
iowrite32(0, base + SATAPHYRESET_REG);
}
static void sata_rcar_gen1_phy_write(struct sata_rcar_priv *priv, u16 reg,
u32 val, int group)
{
void __iomem *base = priv->base;
int timeout;
/* deassert reset */
iowrite32(0, base + SATAPHYRESET_REG);
/* lane 1 */
iowrite32(SATAPHYACCEN_PHYLANE, base + SATAPHYACCEN_REG);
/* write phy register value */
iowrite32(val, base + SATAPHYWDATA_REG);
/* set register group */
if (group)
reg |= SATAPHYADDR_PHYRATEMODE;
/* write command */
iowrite32(SATAPHYADDR_PHYCMD_WRITE | reg, base + SATAPHYADDR_REG);
/* wait for ack */
for (timeout = 0; timeout < 100; timeout++) {
val = ioread32(base + SATAPHYACK_REG);
if (val & SATAPHYACK_PHYACK)
break;
}
if (timeout >= 100)
pr_err("%s timeout\n", __func__);
/* idle state */
iowrite32(0, base + SATAPHYADDR_REG);
}
static void sata_rcar_gen1_phy_init(struct sata_rcar_priv *priv)
{
sata_rcar_gen1_phy_preinit(priv);
sata_rcar_gen1_phy_write(priv, SATAPCTLR1_REG, 0x00200188, 0);
sata_rcar_gen1_phy_write(priv, SATAPCTLR1_REG, 0x00200188, 1);
sata_rcar_gen1_phy_write(priv, SATAPCTLR3_REG, 0x0000A061, 0);
sata_rcar_gen1_phy_write(priv, SATAPCTLR2_REG, 0x20000000, 0);
sata_rcar_gen1_phy_write(priv, SATAPCTLR2_REG, 0x20000000, 1);
sata_rcar_gen1_phy_write(priv, SATAPCTLR4_REG, 0x28E80000, 0);
}
static void sata_rcar_gen2_phy_init(struct sata_rcar_priv *priv)
{
void __iomem *base = priv->base;
iowrite32(RCAR_GEN2_PHY_CTL1, base + RCAR_GEN2_PHY_CTL1_REG);
iowrite32(RCAR_GEN2_PHY_CTL2, base + RCAR_GEN2_PHY_CTL2_REG);
iowrite32(RCAR_GEN2_PHY_CTL3, base + RCAR_GEN2_PHY_CTL3_REG);
iowrite32(RCAR_GEN2_PHY_CTL4, base + RCAR_GEN2_PHY_CTL4_REG);
iowrite32(RCAR_GEN2_PHY_CTL5
|