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/*
* Calxeda Highbank AHCI SATA platform driver
* Copyright 2012 Calxeda, Inc.
*
* based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <linux/kernel.h>
#include <linux/gfp.h>
#include <linux/module.h>
#include <linux/types.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/spinlock.h>
#include <linux/device.h>
#include <linux/of_device.h>
#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/libata.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/export.h>
#include <linux/gpio.h>
#include <linux/of_gpio.h>
#include "ahci.h"
#define CPHY_MAP(dev, addr) ((((dev) & 0x1f) << 7) | (((addr) >> 9) & 0x7f))
#define CPHY_ADDR(addr) (((addr) & 0x1ff) << 2)
#define SERDES_CR_CTL 0x80a0
#define SERDES_CR_ADDR 0x80a1
#define SERDES_CR_DATA 0x80a2
#define CR_BUSY 0x0001
#define CR_START 0x0001
#define CR_WR_RDN 0x0002
#define CPHY_TX_INPUT_STS 0x2001
#define CPHY_RX_INPUT_STS 0x2002
#define CPHY_SATA_TX_OVERRIDE 0x8000
#define CPHY_SATA_RX_OVERRIDE 0x4000
#define CPHY_TX_OVERRIDE 0x2004
#define CPHY_RX_OVERRIDE 0x2005
#define SPHY_LANE 0x100
#define SPHY_HALF_RATE 0x0001
#define CPHY_SATA_DPLL_MODE 0x0700
#define CPHY_SATA_DPLL_SHIFT 8
#define CPHY_SATA_DPLL_RESET (1 << 11)
#define CPHY_SATA_TX_ATTEN 0x1c00
#define CPHY_SATA_TX_ATTEN_SHIFT 10
#define CPHY_PHY_COUNT 6
#define CPHY_LANE_COUNT 4
#define CPHY_PORT_COUNT (CPHY_PHY_COUNT * CPHY_LANE_COUNT)
static DEFINE_SPINLOCK(cphy_lock);
/* Each of the 6 phys can have up to 4 sata ports attached to i. Map 0-based
* sata ports to their phys and then to their lanes within the phys
*/
struct phy_lane_info {
void __iomem *phy_base;
u8 lane_mapping;
u8 phy_devs;
u8 tx_atten;
};
static struct phy_lane_info port_data[CPHY_PORT_COUNT];
static DEFINE_SPINLOCK(sgpio_lock);
#define SCLOCK 0
#define SLOAD 1
#define SDATA 2
#define SGPIO_PINS 3
#define SGPIO_PORTS 8
struct ecx_plat_data {
u32 n_ports;
/* number of extra clocks that the SGPIO PIC controller expects */
u32 pre_clocks;
u32 post_clocks;
unsigned sgpio_gpio[SGPIO_PINS];
u32 sgpio_pattern;
u32 port_to_sgpio[SGPIO_PORTS];
};
#define SGPIO_SIGNALS 3
#define ECX_ACTIVITY_BITS 0x300000
#define ECX_ACTIVITY_SHIFT 0
#define ECX_LOCATE_BITS 0x80000
#define ECX_LOCATE_SHIFT 1
#define ECX_FAULT_BITS 0x400000
#define ECX_FAULT_SHIFT 2
static inline int sgpio_bit_shift(struct ecx_plat_data *pdata, u32 port,
u32 shift)
{
return 1 << (3 * pdata->port_to_sgpio[port] + shift);
}
static void ecx_parse_sgpio(struct ecx_plat_data *pdata, u32 port, u32 state)
{
if (state & ECX_ACTIVITY_BITS)
pdata->sgpio_pattern |= sgpio_bit_shift(pdata, port,
ECX_ACTIVITY_SHIFT);
else
pdata->sgpio_pattern &= ~sgpio_bit_shift(pdata, port,
ECX_ACTIVITY_SHIFT);
if (state & ECX_LOCATE_BITS)
pdata->sgpio_pattern |= sgpio_bit_shift(pdata, port,
ECX_LOCATE_SHIFT);
else
pdata->sgpio_pattern &= ~sgpio_bit_shift(pdata, port,
ECX_LOCATE_SHIFT);
if (state & ECX_FAULT_BITS)
pdata->sgpio_pattern |= sgpio_bit_shift(pdata, port,
ECX_FAULT_SHIFT);
else
pdata->sgpio_pattern &= ~sgpio_bit_shift(pdata, port,
ECX_FAULT_SHIFT);
}
/*
* Tell the LED controller that the signal has changed by raising the clock
* line for 50 uS and then lowering it for 50 uS.
*/
static void ecx_led_cycle_clock(struct ecx_plat_data *pdata)
{
gpio_set_value(pdata->sgpio_gpio[SCLOCK], 1);
udelay(50);
gpio_set_value(pdata->sgpio_gpio[SCLOCK], 0);
udelay(50);
}
static ssize_t ecx_transmit_led_message(struct ata_port *ap, u32 state,
ssize_t size)
{
struct ahci_host_priv *hpriv = ap->host->private_data;
struct ecx_plat_data *pdata = hpriv->plat_data;
struct ahci_port_priv *pp = ap->private_data;
unsigned long flags;
int pmp, i;
struct ahci_em_priv *emp;
u32 sgpio_out;
/* get the slot number from the message */
pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
if (pmp < EM_MAX_SLOTS)
emp = &pp->em_priv[pmp];
else
return -EINVAL;
if (!(hpriv->em_msg_type & EM_MSG_TYPE_LED))
return size;
spin_lock_irqsave(&sgpio_lock, flags);
ecx_parse_sgpio(pdata, ap->port_no, state);
sgpio_out = pdata->sgpio_pattern;
for (i = 0; i < pdata->pre_clocks; i++)
ecx_led_cycle_clock(pdata);
gpio_set_value(pdata->sgpio_gpio[SLOAD], 1);
ecx_led_cycle_clock(pdata);
gpio_set_value(pdata->sgpio_gpio[SLOAD], 0);
/*
* bit-bang out the SGPIO pattern, by consuming a bit and then
* clocking it out.
*/
for (i = 0; i < (SGPIO_SIGNALS * pdata->n_ports); i++) {
gpio_set_value(pdata->sgpio_gpio[SDATA], sgpio_out & 1);
sgpio_out >>= 1;
ecx_led_cycle_clock(pdata);
}
for (i = 0; i < pdata->post_clocks; i++)
ecx_led_cycle_clock(pdata);
/* save off new led state for port/slot */
emp->led_state = state;
spin_unlock_irqrestore(&sgpio_lock, flags);
return size;
}
static void highbank_set_em_messages(struct device *dev,
struct ahci_host_priv *hpriv,
struct ata_port_info *pi)
{
struct device_node *np = dev->of_node;
struct ecx_plat_data *pdata = hpriv->plat_data;
int i;
int err;
for (i = 0; i < SGPIO_PINS; i++) {
err = of_get_named_gpio(np, "calxeda,sgpio-gpio", i);
if (IS_ERR_VALUE(err))
return;
pdata->sgpio_gpio[i] = err;
err = gpio_request(pdata->sgpio_gpio[i], "CX SGPIO");
if (err) {
pr_err("sata_highbank gpio_request %d failed: %d\n",
i, err);
return;
}
gpio_direction_output(pdata->sgpio_gpio[i], 1);
}
of_property_read_u32_array(np, "calxeda,led-order",
pdata->port_to_sgpio,
pdata->n_ports);
if (of_property_read_u32(np, "calxeda,pre-clocks", &pdata->pre_clocks))
pdata->pre_clocks = 0;
if (of_property_read_u32(np, "calxeda,post-clocks",
&pdata->post_clocks))
pdata->post_clocks = 0;
/* store em_loc */
hpriv->em_loc = 0;
hpriv->em_buf_sz = 4;
hpriv->em_msg_type = EM_MSG_TYPE_LED;
pi->flags |= ATA_FLAG_EM | ATA_FLAG_SW_ACTIVITY;
}
static u32 __combo_phy_reg_read(u8 sata_port, u32 addr)
{
u32 data;
u8 dev = port_data[sata_port].phy_devs;
spin_lock(&cphy_lock);
writel(CPHY_MAP(dev, addr), port_data[sata_port].phy_base + 0x800);
data = readl(port_data[sata_port].
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