path: root/drivers/ata/pata_arasan_cf.c

/*
 * drivers/ata/pata_arasan_cf.c
 *
 * Arasan Compact Flash host controller source file
 *
 * Copyright (C) 2011 ST Microelectronics
 * Viresh Kumar <vireshk@kernel.org>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2. This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

/*
 * The Arasan CompactFlash Device Controller IP core has three basic modes of
 * operation: PC card ATA using I/O mode, PC card ATA using memory mode, PC card
 * ATA using true IDE modes. This driver supports only True IDE mode currently.
 *
 * Arasan CF Controller shares global irq register with Arasan XD Controller.
 *
 * Tested on arch/arm/mach-spear13xx
 */

#include <linux/ata.h>
#include <linux/clk.h>
#include <linux/completion.h>
#include <linux/delay.h>
#include <linux/dmaengine.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/libata.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/pata_arasan_cf_data.h>
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/types.h>
#include <linux/workqueue.h>

#define DRIVER_NAME	"arasan_cf"
#define TIMEOUT		msecs_to_jiffies(3000)

/* Registers */
/* CompactFlash Interface Status */
#define CFI_STS			0x000
	#define STS_CHG				(1)
	#define BIN_AUDIO_OUT			(1 << 1)
	#define CARD_DETECT1			(1 << 2)
	#define CARD_DETECT2			(1 << 3)
	#define INP_ACK				(1 << 4)
	#define CARD_READY			(1 << 5)
	#define IO_READY			(1 << 6)
	#define B16_IO_PORT_SEL			(1 << 7)
/* IRQ */
#define IRQ_STS			0x004
/* Interrupt Enable */
#define IRQ_EN			0x008
	#define CARD_DETECT_IRQ			(1)
	#define STATUS_CHNG_IRQ			(1 << 1)
	#define MEM_MODE_IRQ			(1 << 2)
	#define IO_MODE_IRQ			(1 << 3)
	#define TRUE_IDE_MODE_IRQ		(1 << 8)
	#define PIO_XFER_ERR_IRQ		(1 << 9)
	#define BUF_AVAIL_IRQ			(1 << 10)
	#define XFER_DONE_IRQ			(1 << 11)
	#define IGNORED_IRQS	(STATUS_CHNG_IRQ | MEM_MODE_IRQ | IO_MODE_IRQ |\
					TRUE_IDE_MODE_IRQ)
	#define TRUE_IDE_IRQS	(CARD_DETECT_IRQ | PIO_XFER_ERR_IRQ |\
					BUF_AVAIL_IRQ | XFER_DONE_IRQ)
/* Operation Mode */
#define OP_MODE			0x00C
	#define CARD_MODE_MASK			(0x3)
	#define MEM_MODE			(0x0)
	#define IO_MODE				(0x1)
	#define TRUE_IDE_MODE			(0x2)

	#define CARD_TYPE_MASK			(1 << 2)
	#define CF_CARD				(0)
	#define CF_PLUS_CARD			(1 << 2)

	#define CARD_RESET			(1 << 3)
	#define CFHOST_ENB			(1 << 4)
	#define OUTPUTS_TRISTATE		(1 << 5)
	#define ULTRA_DMA_ENB			(1 << 8)
	#define MULTI_WORD_DMA_ENB		(1 << 9)
	#define DRQ_BLOCK_SIZE_MASK		(0x3 << 11)
	#define DRQ_BLOCK_SIZE_512		(0)
	#define DRQ_BLOCK_SIZE_1024		(1 << 11)
	#define DRQ_BLOCK_SIZE_2048		(2 << 11)
	#define DRQ_BLOCK_SIZE_4096		(3 << 11)
/* CF Interface Clock Configuration */
#define CLK_CFG			0x010
	#define CF_IF_CLK_MASK			(0XF)
/* CF Timing Mode Configuration */
#define TM_CFG			0x014
	#define MEM_MODE_TIMING_MASK		(0x3)
	#define MEM_MODE_TIMING_250NS		(0x0)
	#define MEM_MODE_TIMING_120NS		(0x1)
	#define MEM_MODE_TIMING_100NS		(0x2)
	#define MEM_MODE_TIMING_80NS		(0x3)

	#define IO_MODE_TIMING_MASK		(0x3 << 2)
	#define IO_MODE_TIMING_250NS		(0x0 << 2)
	#define IO_MODE_TIMING_120NS		(0x1 << 2)
	#define IO_MODE_TIMING_100NS		(0x2 << 2)
	#define IO_MODE_TIMING_80NS		(0x3 << 2)

	#define TRUEIDE_PIO_TIMING_MASK		(0x7 << 4)
	#define TRUEIDE_PIO_TIMING_SHIFT	4

	#define TRUEIDE_MWORD_DMA_TIMING_MASK	(0x7 << 7)
	#define TRUEIDE_MWORD_DMA_TIMING_SHIFT	7

	#define ULTRA_DMA_TIMING_MASK		(0x7 << 10)
	#define ULTRA_DMA_TIMING_SHIFT		10
/* CF Transfer Address */
#define XFER_ADDR		0x014
	#define XFER_ADDR_MASK			(0x7FF)
	#define MAX_XFER_COUNT			0x20000u
/* Transfer Control */
#define XFER_CTR		0x01C
	#define XFER_COUNT_MASK			(0x3FFFF)
	#define ADDR_INC_DISABLE		(1 << 24)
	#define XFER_WIDTH_MASK			(1 << 25)
	#define XFER_WIDTH_8B			(0)
	#define XFER_WIDTH_16B			(1 << 25)

	#define MEM_TYPE_MASK			(1 << 26)
	#define MEM_TYPE_COMMON			(0)
	#define MEM_TYPE_ATTRIBUTE		(1 << 26)

	#define MEM_IO_XFER_MASK		(1 << 27)
	#define MEM_XFER			(0)
	#define IO_XFER				(1 << 27)

	#define DMA_XFER_MODE			(1 << 28)

	#define AHB_BUS_NORMAL_PIO_OPRTN	(~(1 << 29))
	#define XFER_DIR_MASK			(1 << 30)
	#define XFER_READ			(0)
	#define XFER_WRITE			(1 << 30)

	#define XFER_START			(1 << 31)
/* Write Data Port */
#define WRITE_PORT		0x024
/* Read Data Port */
#define READ_PORT		0x028
/* ATA Data Port */
#define ATA_DATA_PORT		0x030
	#define ATA_DATA_PORT_MASK		(0xFFFF)
/* ATA Error/Features */
#define ATA_ERR_FTR		0x034
/* ATA Sector Count */
#define ATA_SC			0x038
/* ATA Sector Number */
#define ATA_SN			0x03C
/* ATA Cylinder Low */
#define ATA_CL			0x040
/* ATA Cylinder High */
#define ATA_CH			0x044
/* ATA Select Card/Head */
#define ATA_SH			0x048
/* ATA Status-Command */
#define ATA_STS_CMD		0x04C
/* ATA Alternate Status/Device Control */
#define ATA_ASTS_DCTR		0x050
/* Extended Write Data Port 0x200-0x3FC */
#define EXT_WRITE_PORT		0x200
/* Extended Read Data Port 0x400-0x5FC */
#define EXT_READ_PORT		0x400
	#define FIFO_SIZE	0x200u
/* Global Interrupt Status */
#define GIRQ_STS		0x800
/* Global Interrupt Status enable */
#define GIRQ_STS_EN		0x804
/* Global Interrupt Signal enable */
#define GIRQ_SGN_EN		0x808
	#define GIRQ_CF		(1)
	#define GIRQ_XD		(1 << 1)

/* Compact Flash Controller Dev Structure */
struct arasan_cf_dev {
	/* pointer to ata_host structure */
	struct ata_host *host;
	/* clk structure */
	struct clk *clk;

	/* physical base address of controller */
	dma_addr_t pbase;
	/* virtual base address of controller */
	void __iomem *vbase;
	/* irq number*/
	int irq;

	/* status to be updated to framework regarding DMA transfer */
	u8 dma_status;
	/* Card is present or Not */
	u8 card_present;

	/* dma specific */
	/* Completion for transfer complete interrupt from controller */
	struct completion cf_completion;
	/* Completion for DMA transfer complete. */
	struct completion dma_completion;
	/* Dma channel allocated */
	struct dma_chan *dma_chan;
	/* Mask for DMA transfers */
	dma_cap_mask_t mask;
	/* DMA transfer work */
	struct work_struct work;
	/* DMA delayed finish work */
	struct delayed_work dwork;
	/* qc to be transferred using DMA */
	struct ata_queued_cmd *qc;
};

static struct scsi_host_template arasan_cf_sht = {
	ATA_BASE_SHT(DRIVER_NAME),
	.dma_boundary = 0xFFFFFFFFUL,
};

static void cf_dumpregs(struct arasan_cf_dev *acdev)
{
	struct device *dev = acdev->host->dev;

	dev_dbg(dev, ": =========== REGISTER DUMP ===========");
	dev_dbg(dev, ": CFI_STS: %x", readl(acdev->vbase + CFI_STS));
	dev_dbg(dev, ": IRQ_STS: %x", readl(acdev->vbase + IRQ_STS));
	dev_dbg(dev, ": IRQ_EN: %x", readl(acdev->vbase + IRQ_EN));
	dev_dbg(dev, ": OP_MODE: %x", readl(acdev->vbase + OP_MODE));
	dev_dbg(dev, ": CLK_CFG: %x", readl(acdev->vbase + CLK_CFG));
	dev_dbg(dev, ": TM_CFG: %x", readl(acdev->vbase + TM_CFG));
	dev_dbg(dev, ": XFER_CTR: %x", readl(acdev->vbase + XFER_CTR));
	dev_dbg(dev, ": GIRQ_STS: %x", readl(acdev->vbase + GIRQ_STS));
	dev_dbg(dev, ": GIRQ_STS_EN: %x", readl(acdev->vbase + GIRQ_STS_EN));
	dev_dbg(dev, ": GIRQ_SGN_EN: %x", readl(acdev->vbase + GIRQ_SGN_EN));
	dev_dbg(dev, ": =====================================");
}

/* Enable/Disable global interrupts shared between CF and XD ctrlr. */
static void cf_ginterrupt_enable(struct arasan_cf_dev *acdev, bool enable