path: root/arch/sparc/kernel/leon_pci_grpci2.c

// SPDX-License-Identifier: GPL-2.0
/*
 * leon_pci_grpci2.c: GRPCI2 Host PCI driver
 *
 * Copyright (C) 2011 Aeroflex Gaisler AB, Daniel Hellstrom
 *
 */

#include <linux/of_device.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/export.h>
#include <asm/io.h>
#include <asm/leon.h>
#include <asm/vaddrs.h>
#include <asm/sections.h>
#include <asm/leon_pci.h>

#include "irq.h"

struct grpci2_barcfg {
	unsigned long pciadr;	/* PCI Space Address */
	unsigned long ahbadr;	/* PCI Base address mapped to this AHB addr */
};

/* Device Node Configuration options:
 *  - barcfgs    : Custom Configuration of Host's 6 target BARs
 *  - irq_mask   : Limit which PCI interrupts are enabled
 *  - do_reset   : Force PCI Reset on startup
 *
 * barcfgs
 * =======
 *
 * Optional custom Target BAR configuration (see struct grpci2_barcfg). All
 * addresses are physical. Array always contains 6 elements (len=2*4*6 bytes)
 *
 * -1 means not configured (let host driver do default setup).
 *
 * [i*2+0] = PCI Address of BAR[i] on target interface
 * [i*2+1] = Accessing PCI address of BAR[i] result in this AMBA address
 *
 *
 * irq_mask
 * ========
 *
 * Limit which PCI interrupts are enabled. 0=Disable, 1=Enable. By default
 * all are enabled. Use this when PCI interrupt pins are floating on PCB.
 * int, len=4.
 *  bit0 = PCI INTA#
 *  bit1 = PCI INTB#
 *  bit2 = PCI INTC#
 *  bit3 = PCI INTD#
 *
 *
 * reset
 * =====
 *
 * Force PCI reset on startup. int, len=4
 */

/* Enable Debugging Configuration Space Access */
#undef GRPCI2_DEBUG_CFGACCESS

/*
 * GRPCI2 APB Register MAP
 */
struct grpci2_regs {
	unsigned int ctrl;		/* 0x00 Control */
	unsigned int sts_cap;		/* 0x04 Status / Capabilities */
	int res1;			/* 0x08 */
	unsigned int io_map;		/* 0x0C I/O Map address */
	unsigned int dma_ctrl;		/* 0x10 DMA */
	unsigned int dma_bdbase;	/* 0x14 DMA */
	int res2[2];			/* 0x18 */
	unsigned int bars[6];		/* 0x20 read-only PCI BARs */
	int res3[2];			/* 0x38 */
	unsigned int ahbmst_map[16];	/* 0x40 AHB->PCI Map per AHB Master */

	/* PCI Trace Buffer Registers (OPTIONAL) */
	unsigned int t_ctrl;		/* 0x80 */
	unsigned int t_cnt;		/* 0x84 */
	unsigned int t_adpat;		/* 0x88 */
	unsigned int t_admask;		/* 0x8C */
	unsigned int t_sigpat;		/* 0x90 */
	unsigned int t_sigmask;		/* 0x94 */
	unsigned int t_adstate;		/* 0x98 */
	unsigned int t_sigstate;	/* 0x9C */
};

#define REGLOAD(a)	(be32_to_cpu(__raw_readl(&(a))))
#define REGSTORE(a, v)	(__raw_writel(cpu_to_be32(v), &(a)))

#define CTRL_BUS_BIT 16

#define CTRL_RESET (1<<31)
#define CTRL_SI (1<<27)
#define CTRL_PE (1<<26)
#define CTRL_EI (1<<25)
#define CTRL_ER (1<<24)
#define CTRL_BUS (0xff<<CTRL_BUS_BIT)
#define CTRL_HOSTINT 0xf

#define STS_HOST_BIT	31
#define STS_MST_BIT	30
#define STS_TAR_BIT	29
#define STS_DMA_BIT	28
#define STS_DI_BIT	27
#define STS_HI_BIT	26
#define STS_IRQMODE_BIT	24
#define STS_TRACE_BIT	23
#define STS_CFGERRVALID_BIT 20
#define STS_CFGERR_BIT	19
#define STS_INTTYPE_BIT	12
#define STS_INTSTS_BIT	8
#define STS_FDEPTH_BIT	2
#define STS_FNUM_BIT	0

#define STS_HOST	(1<<STS_HOST_BIT)
#define STS_MST		(1<<STS_MST_BIT)
#define STS_TAR		(1<<STS_TAR_BIT)
#define STS_DMA		(1<<STS_DMA_BIT)
#define STS_DI		(1<<STS_DI_BIT)
#define STS_HI		(1<<STS_HI_BIT)
#define STS_IRQMODE	(0x3<<STS_IRQMODE_BIT)
#define STS_TRACE	(1<<STS_TRACE_BIT)
#define STS_CFGERRVALID	(1<<STS_CFGERRVALID_BIT)
#define STS_CFGERR	(1<<STS_CFGERR_BIT)
#define STS_INTTYPE	(0x3f<<STS_INTTYPE_BIT)
#define STS_INTSTS	(0xf<<STS_INTSTS_BIT)
#define STS_FDEPTH	(0x7<<STS_FDEPTH_BIT)
#define STS_FNUM	(0x3<<STS_FNUM_BIT)

#define STS_ISYSERR	(1<<17)
#define STS_IDMA	(1<<16)
#define STS_IDMAERR	(1<<15)
#define STS_IMSTABRT	(1<<14)
#define STS_ITGTABRT	(1<<13)
#define STS_IPARERR	(1<<12)

#define STS_ERR_IRQ (STS_ISYSERR | STS_IMSTABRT | STS_ITGTABRT | STS_IPARERR)

struct grpci2_bd_chan {
	unsigned int ctrl;	/* 0x00 DMA Control */
	unsigned int nchan;	/* 0x04 Next DMA Channel Address */
	unsigned int nbd;	/* 0x08 Next Data Descriptor in chan */
	unsigned int res;	/* 0x0C Reserved */
};

#define BD_CHAN_EN		0x80000000
#define BD_CHAN_TYPE		0x00300000
#define BD_CHAN_BDCNT		0x0000ffff
#define BD_CHAN_EN_BIT		31
#define BD_CHAN_TYPE_BIT	20
#define BD_CHAN_BDCNT_BIT	0

struct grpci2_bd_data {
	unsigned int ctrl;	/* 0x00 DMA Data Control */
	unsigned int pci_adr;	/* 0x04 PCI Start Address */
	unsigned int ahb_adr;	/* 0x08 AHB Start address */
	unsigned int next;	/* 0x0C Next Data Descriptor in chan */
};

#define BD_DATA_EN		0x80000000
#define BD_DATA_IE		0x40000000
#define BD_DATA_DR		0x20000000
#define BD_DATA_TYPE		0x00300000
#define BD_DATA_ER		0x00080000
#define BD_DATA_LEN		0x0000ffff
#define BD_DATA_EN_BIT		31
#define BD_DATA_IE_BIT		30
#define BD_DATA_DR_BIT		29
#define BD_DATA_TYPE_BIT	20
#define BD_DATA_ER_BIT		19
#define BD_DATA_LEN_BIT		0

/* GRPCI2 Capability */
struct grpci2_cap_first {
	unsigned int ctrl;
	unsigned int pci2ahb_map[6];
	unsigned int ext2ahb_map;
	unsigned int io_map;
	unsigned int pcibar_size[6];
};
#define CAP9_CTRL_OFS 0
#define CAP9_BAR_OFS 0x4
#define CAP9_IOMAP_OFS 0x20
#define CAP9_BARSIZE_OFS 0x24

#define TGT 256

struct grpci2_priv {
	struct leon_pci_info	info; /* must be on top of this structure */
	struct grpci2_regs __iomem *regs;
	char			irq;
	char			irq_mode; /* IRQ Mode from CAPSTS REG */
	char			bt_enabled;
	char			do_reset;
	char			irq_mask;
	u32			pciid; /* PCI ID of Host */
	unsigned char		irq_map[4];

	/* Virtual IRQ numbers */
	unsigned int		virq_err;
	unsigned int		virq_dma;

	/* AHB PCI Windows */
	unsigned long		pci_area;	/* MEMORY */
	unsigned long		pci_area_end;
	unsigned long		pci_io;		/* I/O */
	unsigned long		pci_conf;	/* CONFIGURATION */
	unsigned long		pci_conf_end;
	unsigned long		pci_io_va;

	struct grpci2_barcfg	tgtbars[6];
};

static DEFINE_SPINLOCK(grpci2_dev_lock);
static struct grpci2_priv *grpci2priv;

static int grpci2_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
	struct grpci2_priv *priv = dev->bus->sysdata;
	int irq_group;

	/* Use default IRQ decoding on PCI BUS0 according slot numbering */
	irq_group = slot & 0x3;
	pin = ((pin - 1) + irq_group) & 0x3;

	return priv->irq_map[pin];
}

static int grpci2_cfg_r32(struct grpci2_priv *priv, unsigned int bus,
				unsigned int devfn, int where, u32 *val)
{
	unsigned int *pci_conf;
	unsigned long flags;
	u32 tmp;

	if (where & 0x3)
		return -EINVAL;

	if (bus == 0) {
		devfn += (0x8 * 6); /* start at AD16=Device0 */
	} else if (bus == TGT)