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/*
* Ethernet driver for Motorola MPC8xx.
* Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
*
* I copied the basic skeleton from the lance driver, because I did not
* know how to write the Linux driver, but I did know how the LANCE worked.
*
* This version of the driver is somewhat selectable for the different
* processor/board combinations. It works for the boards I know about
* now, and should be easily modified to include others. Some of the
* configuration information is contained in <asm/cpm1.h> and the
* remainder is here.
*
* Buffer descriptors are kept in the CPM dual port RAM, and the frame
* buffers are in the host memory.
*
* Right now, I am very watseful with the buffers. I allocate memory
* pages and then divide them into 2K frame buffers. This way I know I
* have buffers large enough to hold one frame within one buffer descriptor.
* Once I get this working, I will use 64 or 128 byte CPM buffers, which
* will be much more memory efficient and will easily handle lots of
* small packets.
*
*/
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/string.h>
#include <linux/ptrace.h>
#include <linux/errno.h>
#include <linux/ioport.h>
#include <linux/slab.h>
#include <linux/interrupt.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/skbuff.h>
#include <linux/spinlock.h>
#include <linux/dma-mapping.h>
#include <linux/bitops.h>
#include <asm/8xx_immap.h>
#include <asm/pgtable.h>
#include <asm/mpc8xx.h>
#include <asm/uaccess.h>
#include <asm/cpm1.h>
#include <asm/cacheflush.h>
/*
* Theory of Operation
*
* The MPC8xx CPM performs the Ethernet processing on SCC1. It can use
* an aribtrary number of buffers on byte boundaries, but must have at
* least two receive buffers to prevent constant overrun conditions.
*
* The buffer descriptors are allocated from the CPM dual port memory
* with the data buffers allocated from host memory, just like all other
* serial communication protocols. The host memory buffers are allocated
* from the free page pool, and then divided into smaller receive and
* transmit buffers. The size of the buffers should be a power of two,
* since that nicely divides the page. This creates a ring buffer
* structure similar to the LANCE and other controllers.
*
* Like the LANCE driver:
* The driver runs as two independent, single-threaded flows of control. One
* is the send-packet routine, which enforces single-threaded use by the
* cep->tx_busy flag. The other thread is the interrupt handler, which is
* single threaded by the hardware and other software.
*
* The send packet thread has partial control over the Tx ring and the
* 'cep->tx_busy' flag. It sets the tx_busy flag whenever it's queuing a Tx
* packet. If the next queue slot is empty, it clears the tx_busy flag when
* finished otherwise it sets the 'lp->tx_full' flag.
*
* The MBX has a control register external to the MPC8xx that has some
* control of the Ethernet interface. Information is in the manual for
* your board.
*
* The RPX boards have an external control/status register. Consult the
* programming documents for details unique to your board.
*
* For the TQM8xx(L) modules, there is no control register interface.
* All functions are directly controlled using I/O pins. See <asm/cpm1.h>.
*/
/* The transmitter timeout
*/
#define TX_TIMEOUT (2*HZ)
/* The number of Tx and Rx buffers. These are allocated from the page
* pool. The code may assume these are power of two, so it is best
* to keep them that size.
* We don't need to allocate pages for the transmitter. We just use
* the skbuffer directly.
*/
#ifdef CONFIG_ENET_BIG_BUFFERS
#define CPM_ENET_RX_PAGES 32
#define CPM_ENET_RX_FRSIZE 2048
#define CPM_ENET_RX_FRPPG (PAGE_SIZE / CPM_ENET_RX_FRSIZE)
#define RX_RING_SIZE (CPM_ENET_RX_FRPPG * CPM_ENET_RX_PAGES)
#define TX_RING_SIZE 64 /* Must be power of two */
#define TX_RING_MOD_MASK 63 /* for this to work */
#else
#define CPM_ENET_RX_PAGES 4
#define CPM_ENET_RX_FRSIZE 2048
#define CPM_ENET_RX_FRPPG (PAGE_SIZE / CPM_ENET_RX_FRSIZE)
#define RX_RING_SIZE (CPM_ENET_RX_FRPPG * CPM_ENET_RX_PAGES)
#define TX_RING_SIZE 8 /* Must be power of two */
#define TX_RING_MOD_MASK 7 /* for this to work */
#endif
/* The CPM stores dest/src/type, data, and checksum for receive packets.
*/
#define PKT_MAXBUF_SIZE 1518
#define PKT_MINBUF_SIZE 64
#define PKT_MAXBLR_SIZE 1520
/* The CPM buffer descriptors track the ring buffers. The rx_bd_base and
* tx_bd_base always point to the base of the buffer descriptors. The
* cur_rx and cur_tx point to the currently available buffer.
* The dirty_tx tracks the current buffer that is being sent by the
* controller. The cur_tx and dirty_tx are equal under both completely
* empty and completely full conditions. The empty/ready indicator in
* the buffer descriptor determines the actual condition.
*/
struct scc_enet_private {
/* The saved address of a sent-in-place packet/buffer, for skfree(). */
struct sk_buff* tx_skbuff[TX_RING_SIZE];
ushort skb_cur;
ushort skb_dirty;
/* CPM dual port RAM relative addresses.
*/
cbd_t *rx_bd_base; /* Address of Rx and Tx buffers. */
cbd_t *tx_bd_base;
cbd_t *cur_rx, *cur_tx; /* The next free ring entry */
cbd_t *dirty_tx; /* The ring entries to be free()ed. */
scc_t *sccp;
/* Virtual addresses for the receive buffers because we can't
* do a __va() on them anymore.
*/
unsigned char *rx_vaddr[RX_RING_SIZE];
struct net_device_stats stats;
uint tx_full;
spinlock_t lock;
};
static int scc_enet_open(struct net_device *dev);
static int scc_enet_start_xmit(struct sk_buff *skb, struct net_device *dev);
static int scc_enet_rx(struct net_device *dev);
static void scc_enet_interrupt(void *dev_id);
static int scc_enet_close(struct net_device *dev);
static struct net_device_stats *scc_enet_get_stats(struct net_device *dev);
static void set_multicast_list(struct net_device *dev);
/* Get this from various configuration locations (depends on board).
*/
/*static ushort my_enet_addr[] = { 0x0800, 0x3e26, 0x1559 };*/
/* Typically, 860(T) boards use SCC1 for Ethernet, and other 8xx boards
* use SCC2. Some even may use SCC3.
* This is easily extended if necessary.
*/
#if defined(CONFIG_SCC3_ENET)
#define CPM_CR_ENET CPM_CR_CH_SCC3
#define PROFF_ENET PROFF_SCC3
#define SCC_ENET 2 /* Index, not number! */
#define CPMVEC_ENET CPMVEC_SCC3
#elif defined(CONFIG_SCC2_ENET)
#define CPM_CR_ENET CPM_CR_CH_SCC2
#define PROFF_ENET PROFF_SCC2
#define SCC_ENET 1 /* Index, not number! */
#define CPMVEC_ENET CPMVEC_SCC2
#elif defined(CONFIG_SCC1_ENET)
#define CPM_CR_ENET CPM_CR_CH_SCC1
#define PROFF_ENET PROFF_SCC1
#define SCC_ENET 0 /* Index, not number! */
#define CPMVEC_ENET CPMVEC_SCC1
#else
#error CONFIG_SCCx_ENET not defined
#endif
static int
scc_enet_open(struct net_device *dev)
{
/* I should reset the ring buffers here, but I don't yet know
* a simple way to do that.
*/
netif_start_queue(dev);
return 0; /* Always succeed */
}
static int
scc_enet_start_xmit(struct sk_buff *skb, struct net_device *dev)
{
struct scc_enet_private *cep = (struct scc_enet_private *)dev->priv;
volatile cbd_t *bdp;
/* Fill in a Tx ring entry */
bdp = cep->cur_tx;
#ifndef final_version
if (bdp->cbd_sc & BD_ENET_TX_READY) {
/* Ooops. All transmit buffers are full. Bail out.
* This should not happen, since cep->tx_busy should be set.
*/
printk("%s: tx queue full!.\n", dev->name);
return 1;
}
#endif
/* Clear all of the status flags.
*/
bdp->cbd_sc &= ~BD_ENET_TX_STATS;
/* If the frame is short, tell CPM to pad it.
*/
if (skb->len <= ETH_ZLEN)
bdp->cbd_sc |= BD_ENET_TX_PAD;
else
bdp->cbd_sc &= ~BD_ENET_TX_PAD;
/* Set buffer length and buffer pointer.
*/
bdp->cbd_datlen = skb->len;
bdp->cbd_bufaddr = __pa(skb->data);
/* Save skb pointer.
*/
cep->tx_skbuff[cep->skb_cur] = skb;
cep->stats.tx_bytes += skb->len;
cep->skb_cur = (cep->skb_cur+1) & TX_RING_MOD_MASK;
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