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// SPDX-License-Identifier: GPL-2.0+
/*
* TCE helpers for IODA PCI/PCIe on PowerNV platforms
*
* Copyright 2018 IBM Corp.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*/
#include <linux/kernel.h>
#include <linux/iommu.h>
#include <asm/iommu.h>
#include <asm/tce.h>
#include "pci.h"
void pnv_pci_setup_iommu_table(struct iommu_table *tbl,
void *tce_mem, u64 tce_size,
u64 dma_offset, unsigned int page_shift)
{
tbl->it_blocksize = 16;
tbl->it_base = (unsigned long)tce_mem;
tbl->it_page_shift = page_shift;
tbl->it_offset = dma_offset >> tbl->it_page_shift;
tbl->it_index = 0;
tbl->it_size = tce_size >> 3;
tbl->it_busno = 0;
tbl->it_type = TCE_PCI;
}
static __be64 *pnv_alloc_tce_level(int nid, unsigned int shift)
{
struct page *tce_mem = NULL;
__be64 *addr;
tce_mem = alloc_pages_node(nid, GFP_KERNEL, shift - PAGE_SHIFT);
if (!tce_mem) {
pr_err("Failed to allocate a TCE memory, level shift=%d\n",
shift);
return NULL;
}
addr = page_address(tce_mem);
memset(addr, 0, 1UL << shift);
return addr;
}
static __be64 *pnv_tce(struct iommu_table *tbl, bool user, long idx, bool alloc)
{
__be64 *tmp = user ? tbl->it_userspace : (__be64 *) tbl->it_base;
int level = tbl->it_indirect_levels;
const long shift = ilog2(tbl->it_level_size);
unsigned long mask = (tbl->it_level_size - 1) << (level * shift);
while (level) {
int n = (idx & mask) >> (level * shift);
unsigned long tce;
if (tmp[n] == 0) {
__be64 *tmp2;
if (!alloc)
return NULL;
tmp2 = pnv_alloc_tce_level(tbl->it_nid,
ilog2(tbl->it_level_size) + 3);
if (!tmp2)
return NULL;
tmp[n] = cpu_to_be64(__pa(tmp2) |
TCE_PCI_READ | TCE_PCI_WRITE);
}
tce = be64_to_cpu(tmp[n]);
tmp = __va(tce & ~(TCE_PCI_READ | TCE_PCI_WRITE));
idx &= ~mask;
mask >>= shift;
--level;
}
return tmp + idx;
}
int pnv_tce_build(struct iommu_table *tbl, long index, long npages,
unsigned long uaddr, enum dma_data_direction direction,
unsigned long attrs)
{
u64 proto_tce = iommu_direction_to_tce_perm(direction);
u64 rpn = __pa(uaddr) >> tbl->it_page_shift;
long i;
if (proto_tce & TCE_PCI_WRITE)
proto_tce |= TCE_PCI_READ;
for (i = 0; i < npages; i++) {
unsigned long newtce = proto_tce |
((rpn + i) << tbl->it_page_shift);
unsigned long idx = index - tbl->it_offset + i;
*(pnv_tce(tbl, false, idx, true)) = cpu_to_be64(newtce);
}
return 0;
}
#ifdef CONFIG_IOMMU_API
int pnv_tce_xchg(struct iommu_table *tbl, long index,
unsigned long *hpa, enum dma_data_direction *direction,
bool alloc)
{
u64 proto_tce = iommu_direction_to_tce_perm(*direction);
unsigned long newtce = *hpa | proto_tce, oldtce;
unsigned long idx = index - tbl->it_offset;
__be64 *ptce = NULL;
BUG_ON(*hpa & ~IOMMU_PAGE_MASK(tbl));
if (*direction == DMA_NONE) {
ptce = pnv_tce(tbl, false, idx, false);
if (!ptce) {
*hpa = 0;
return 0;
}
}
if (!ptce) {
ptce = pnv_tce(tbl, false, idx, alloc);
if (!ptce)
return alloc ? H_HARDWARE : H_TOO_HARD;
}
if (newtce & TCE_PCI_WRITE)
newtce |= TCE_PCI_READ;
oldtce = be64_to_cpu(xchg(ptce, cpu_to_be64(newtce)));
*hpa = oldtce & ~(TCE_PCI_READ | TCE_PCI_WRITE);
*direction = iommu_tce_direction(oldtce);
return 0;
}
__be64 *pnv_tce_useraddrptr(struct iommu_table *tbl, long index, bool alloc)
{
if (WARN_ON_ONCE(!tbl->it_userspace))
return NULL;
return pnv_tce(tbl, true, index - tbl->it_offset, alloc);
}
#endif
void pnv_tce_free(struct iommu_table *tbl, long index, long npages)
{
long i;
for (i = 0; i < npages; i++) {
unsigned long idx = index - tbl->it_offset + i;
__be64 *ptce = pnv_tce(tbl, false, idx, false);
if (ptce)
*ptce = cpu_to_be64(0);
}
}
unsigned long pnv_tce_get(struct iommu_table *tbl, long index)
{
__be64 *ptce = pnv_tce(tbl, false, index - tbl->it_offset, false);
if (!ptce)
return 0;
return be64_to_cpu(*ptce);
}
static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr,
unsigned long size, unsigned int levels)
{
const unsigned long addr_ul = (unsigned long) addr &
~(TCE_PCI_READ | TCE_PCI_WRITE);
if (levels) {
long i;
u64 *tmp = (u64 *) addr_ul;
for (i = 0; i < size; ++i) {
unsigned long hpa = be64_to_cpu(tmp[i]);
if (!(hpa & (TCE_PCI_READ | TCE_PCI_WRITE)))
continue;
pnv_pci_ioda2_table_do_free_pages(__va(hpa), size,
levels - 1);
}
}
free_pages(addr_ul, get_order(size << 3));
}
void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl)
{
const unsigned long size = tbl->it_indirect_levels ?
tbl->it_level_size : tbl->it_size;
if (!tbl->it_size)
return;
pnv_pci_ioda2_table_do_free_pages((__be64 *)tbl->it_base, size,
tbl->it_indirect_levels);
if (tbl->it_userspace) {
pnv_pci_ioda2_table_do_free_pages(tbl->it_userspace, size,
tbl->it_indirect_levels);
}
}
static __be64 *pnv_pci_ioda2_table_do_alloc_pages(int nid, unsigned int shift,
unsigned int levels, unsigned long limit,
unsigned long *current_offset, unsigned long *total_allocated)
{
__be64 *addr, *tmp;
unsigned long
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