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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Enter and leave deep sleep state on MPC83xx
*
* Copyright (c) 2006-2008 Freescale Semiconductor, Inc.
* Author: Scott Wood <scottwood@freescale.com>
*/
#include <asm/page.h>
#include <asm/ppc_asm.h>
#include <asm/reg.h>
#include <asm/asm-offsets.h>
#define SS_MEMSAVE 0x00 /* First 8 bytes of RAM */
#define SS_HID 0x08 /* 3 HIDs */
#define SS_IABR 0x14 /* 2 IABRs */
#define SS_IBCR 0x1c
#define SS_DABR 0x20 /* 2 DABRs */
#define SS_DBCR 0x28
#define SS_SP 0x2c
#define SS_SR 0x30 /* 16 segment registers */
#define SS_R2 0x70
#define SS_MSR 0x74
#define SS_SDR1 0x78
#define SS_LR 0x7c
#define SS_SPRG 0x80 /* 8 SPRGs */
#define SS_DBAT 0xa0 /* 8 DBATs */
#define SS_IBAT 0xe0 /* 8 IBATs */
#define SS_TB 0x120
#define SS_CR 0x128
#define SS_GPREG 0x12c /* r12-r31 */
#define STATE_SAVE_SIZE 0x17c
.section .data
.align 5
mpc83xx_sleep_save_area:
.space STATE_SAVE_SIZE
immrbase:
.long 0
.section .text
.align 5
/* r3 = physical address of IMMR */
_GLOBAL(mpc83xx_enter_deep_sleep)
lis r4, immrbase@ha
stw r3, immrbase@l(r4)
/* The first 2 words of memory are used to communicate with the
* bootloader, to tell it how to resume.
*
* The first word is the magic number 0xf5153ae5, and the second
* is the pointer to mpc83xx_deep_resume.
*
* The original content of these two words is saved in SS_MEMSAVE.
*/
lis r3, mpc83xx_sleep_save_area@h
ori r3, r3, mpc83xx_sleep_save_area@l
lis r4, KERNELBASE@h
lwz r5, 0(r4)
lwz r6, 4(r4)
stw r5, SS_MEMSAVE+0(r3)
stw r6, SS_MEMSAVE+4(r3)
mfspr r5, SPRN_HID0
mfspr r6, SPRN_HID1
mfspr r7, SPRN_HID2
stw r5, SS_HID+0(r3)
stw r6, SS_HID+4(r3)
stw r7, SS_HID+8(r3)
mfspr r4, SPRN_IABR
mfspr r5, SPRN_IABR2
mfspr r6, SPRN_IBCR
mfspr r7, SPRN_DABR
mfspr r8, SPRN_DABR2
mfspr r9, SPRN_DBCR
stw r4, SS_IABR+0(r3)
stw r5, SS_IABR+4(r3)
stw r6, SS_IBCR(r3)
stw r7, SS_DABR+0(r3)
stw r8, SS_DABR+4(r3)
stw r9, SS_DBCR(r3)
mfspr r4, SPRN_SPRG0
mfspr r5, SPRN_SPRG1
mfspr r6, SPRN_SPRG2
mfspr r7, SPRN_SPRG3
mfsdr1 r8
stw r4, SS_SPRG+0(r3)
stw r5, SS_SPRG+4(r3)
stw r6, SS_SPRG+8(r3)
stw r7, SS_SPRG+12(r3)
stw r8, SS_SDR1(r3)
mfspr r4, SPRN_SPRG4
mfspr r5, SPRN_SPRG5
mfspr r6, SPRN_SPRG6
mfspr r7, SPRN_SPRG7
stw r4, SS_SPRG+16(r3)
stw r5, SS_SPRG+20(r3)
stw r6, SS_SPRG+24(r3)
stw r7, SS_SPRG+28(r3)
mfspr r4, SPRN_DBAT0U
mfspr r5, SPRN_DBAT0L
mfspr r6, SPRN_DBAT1U
mfspr r7, SPRN_DBAT1L
stw r4, SS_DBAT+0x00(r3)
stw r5, SS_DBAT+0x04(r3)
stw r6, SS_DBAT+0x08(r3)
stw r7, SS_DBAT+0x0c(r3)
mfspr r4, SPRN_DBAT2U
mfspr r5, SPRN_DBAT2L
mfspr r6, SPRN_DBAT3U
mfspr r7, SPRN_DBAT3L
stw r4, SS_DBAT+0x10(r3)
stw r5, SS_DBAT+0x14(r3)
stw r6, SS_DBAT+0x18(r3)
stw r7, SS_DBAT+0x1c(r3)
mfspr r4, SPRN_DBAT4U
mfspr r5, SPRN_DBAT4L
mfspr r6, SPRN_DBAT5U
mfspr r7, SPRN_DBAT5L
stw r4, SS_DBAT+0x20(r3)
stw r5, SS_DBAT+0x24(r3)
stw r6, SS_DBAT+0x28(r3)
stw r7, SS_DBAT+0x2c(r3)
mfspr r4, SPRN_DBAT6U
mfspr r5, SPRN_DBAT6L
mfspr r6, SPRN_DBAT7U
mfspr r7, SPRN_DBAT7L
stw r4, SS_DBAT+0x30(r3)
stw r5, SS_DBAT+0x34(r3)
stw r6, SS_DBAT+0x38(r3)
stw r7, SS_DBAT+0x3c(r3)
mfspr r4, SPRN_IBAT0U
mfspr r5, SPRN_IBAT0L
mfspr r6, SPRN_IBAT1U
mfspr r7, SPRN_IBAT1L
stw r4, SS_IBAT+0x00(r3)
stw r5, SS_IBAT+0x04(r3)
stw r6, SS_IBAT+0x08(r3)
stw r7, SS_IBAT+0x0c(r3)
mfspr r4, SPRN_IBAT2U
mfspr r5, SPRN_IBAT2L
mfspr r6, SPRN_IBAT3U
mfspr r7, SPRN_IBAT3L
stw r4, SS_IBAT+0x10(r3)
stw r5, SS_IBAT+0x14(r3)
stw r6, SS_IBAT+0x18(r3)
stw r7, SS_IBAT+0x1c(r3)
mfspr r4, SPRN_IBAT4U
mfspr r5, SPRN_IBAT4L
mfspr r6, SPRN_IBAT5U
mfspr r7, SPRN_IBAT5L
stw r4, SS_IBAT+0x20(r3)
stw r5, SS_IBAT+0x24(r3)
stw r6, SS_IBAT+0x28(r3)
stw r7, SS_IBAT+0x2c(r3)
mfspr r4, SPRN_IBAT6U
mfspr r5, SPRN_IBAT6L
mfspr r6, SPRN_IBAT7U
mfspr r7, SPRN_IBAT7L
stw r4, SS_IBAT+0x30(r3)
stw r5, SS_IBAT+0x34(r3)
stw r6, SS_IBAT+0x38(r3)
stw r7, SS_IBAT+0x3c(r3)
mfmsr r4
mflr r5
mfcr r6
stw r4, SS_MSR(r3)
stw r5, SS_LR(r3)
stw r6, SS_CR(r3)
stw r1, SS_SP(r3)
stw r2, SS_R2(r3)
1: mftbu r4
mftb r5
mftbu r6
cmpw r4, r6
bne 1b
stw r4, SS_TB+0(r3)
stw r5, SS_TB+4(r3)
stmw r12, SS_GPREG(r3)
li r4, 0
addi r6, r3, SS_SR-4
1: mfsrin r5, r4
stwu r5, 4(r6)
addis r4, r4, 0x1000
cmpwi r4, 0
bne 1b
/* Disable machine checks
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