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/*
*
* Programmable Interrupt Controller functions for the Freescale MPC52xx.
*
* Copyright (C) 2008 Secret Lab Technologies Ltd.
* Copyright (C) 2006 bplan GmbH
* Copyright (C) 2004 Sylvain Munaut <tnt@246tNt.com>
* Copyright (C) 2003 Montavista Software, Inc
*
* Based on the code from the 2.4 kernel by
* Dale Farnsworth <dfarnsworth@mvista.com> and Kent Borg.
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*
*/
/*
* This is the device driver for the MPC5200 interrupt controller.
*
* hardware overview
* -----------------
* The MPC5200 interrupt controller groups the all interrupt sources into
* three groups called 'critical', 'main', and 'peripheral'. The critical
* group has 3 irqs, External IRQ0, slice timer 0 irq, and wake from deep
* sleep. Main group include the other 3 external IRQs, slice timer 1, RTC,
* gpios, and the general purpose timers. Peripheral group contains the
* remaining irq sources from all of the on-chip peripherals (PSCs, Ethernet,
* USB, DMA, etc).
*
* virqs
* -----
* The Linux IRQ subsystem requires that each irq source be assigned a
* system wide unique IRQ number starting at 1 (0 means no irq). Since
* systems can have multiple interrupt controllers, the virtual IRQ (virq)
* infrastructure lets each interrupt controller to define a local set
* of IRQ numbers and the virq infrastructure maps those numbers into
* a unique range of the global IRQ# space.
*
* To define a range of virq numbers for this controller, this driver first
* assigns a number to each of the irq groups (called the level 1 or L1
* value). Within each group individual irq sources are also assigned a
* number, as defined by the MPC5200 user guide, and refers to it as the
* level 2 or L2 value. The virq number is determined by shifting up the
* L1 value by MPC52xx_IRQ_L1_OFFSET and ORing it with the L2 value.
*
* For example, the TMR0 interrupt is irq 9 in the main group. The
* virq for TMR0 is calculated by ((1 << MPC52xx_IRQ_L1_OFFSET) | 9).
*
* The observant reader will also notice that this driver defines a 4th
* interrupt group called 'bestcomm'. The bestcomm group isn't physically
* part of the MPC5200 interrupt controller, but it is used here to assign
* a separate virq number for each bestcomm task (since any of the 16
* bestcomm tasks can cause the bestcomm interrupt to be raised). When a
* bestcomm interrupt occurs (peripheral group, irq 0) this driver determines
* which task needs servicing and returns the irq number for that task. This
* allows drivers which use bestcomm to define their own interrupt handlers.
*
* irq_chip structures
* -------------------
* For actually manipulating IRQs (masking, enabling, clearing, etc) this
* driver defines four separate 'irq_chip' structures, one for the main
* group, one for the peripherals group, one for the bestcomm group and one
* for external interrupts. The irq_chip structures provide the hooks needed
* to manipulate each IRQ source, and since each group is has a separate set
* of registers for controlling the irq, it makes sense to divide up the
* hooks along those lines.
*
* You'll notice that there is not an irq_chip for the critical group and
* you'll also notice that there is an irq_chip defined for external
* interrupts even though there is no external interrupt group. The reason
* for this is that the four external interrupts are all managed with the same
* register even though one of the external IRQs is in the critical group and
* the other three are in the main group. For this reason it makes sense for
* the 4 external irqs to be managed using a separate set of hooks. The
* reason there is no crit irq_chip is that of the 3 irqs in the critical
* group, only external interrupt is actually support at this time by this
* driver and since external interrupt is the only one used, it can just
* be directed to make use of the external irq irq_chip.
*
* device tree bindings
* --------------------
* The device tree bindings for this controller reflect the two level
* organization of irqs in the device. #interrupt-cells = <3> where the
* first cell is the group number [0..3], the second cell is the irq
* number in the group, and the third cell is the sense type (level/edge).
* For reference, the following is a list of the interrupt property values
* associated with external interrupt sources on the MPC5200 (just because
* it is non-obvious to determine what the interrupts property should be
* when reading the mpc5200 manual and it is a frequently asked question).
*
* External interrupts:
* <0 0 n> external irq0, n is sense (n=0: level high,
* <1 1 n> external irq1, n is sense n=1: edge rising,
* <1 2 n> external irq2, n is sense n=2: edge falling,
* <1 3 n> external irq3, n is sense n=3: level low)
*/
#undef DEBUG
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/of.h>
#include <asm/io.h>
#include <asm/prom.h>
#include <asm/mpc52xx.h>
/* HW IRQ mapping */
#define MPC52xx_IRQ_L1_CRIT (0)
#define MPC52xx_IRQ_L1_MAIN (1)
#define MPC52xx_IRQ_L1_PERP (2)
#define MPC52xx_IRQ_L1_SDMA (3)
#define MPC52xx_IRQ_L1_OFFSET (6)
#define MPC52xx_IRQ_L1_MASK (0x00c0)
#define MPC52xx_IRQ_L2_MASK (0x003f)
#define MPC52xx_IRQ_HIGHTESTHWIRQ (0xd0)
/* MPC5200 device tree match tables */
static struct of_device_id mpc52xx_pic_ids[] __initdata = {
{ .compatible = "fsl,mpc5200-pic", },
{ .compatible = "mpc5200-pic", },
{}
};
static struct of_device_id mpc52xx_sdma_ids[] __initdata = {
{ .compatible = "fsl,mpc5200-bestcomm", },
{ .compatible = "mpc5200-bestcomm", },
{}
};
static struct mpc52xx_intr __iomem *intr;
static struct mpc52xx_sdma __iomem *sdma;
static struct irq_host *mpc52xx_irqhost = NULL;
static unsigned char mpc52xx_map_senses[4] = {
IRQ_TYPE_LEVEL_HIGH,
IRQ_TYPE_EDGE_RISING,
IRQ_TYPE_EDGE_FALLING,
IRQ_TYPE_LEVEL_LOW,
};
/* Utility functions */
static inline void io_be_setbit(u32 __iomem *addr, int bitno)
{
out_be32(addr, in_be32(addr) | (1 << bitno));
}
static inline void io_be_clrbit(u32 __iomem *addr, int bitno)
{
out_be32(addr, in_be32(addr) & ~(1 << bitno));
}
/*
* IRQ[0-3] interrupt irq_chip
*/
static void mpc52xx_extirq_mask(struct irq_data *d)
{
int irq;
int l2irq;
irq = irq_map[d->irq].hwirq;
l2irq = irq & MPC52xx_IRQ_L2_MASK;
io_be_clrbit(&intr->ctrl, 11 - l2irq);
}
static void mpc52xx_extirq_unmask(struct irq_data *d)
{
int irq;
int l2irq;
irq = irq_map[d->irq].hwirq;
l2irq = irq & MPC52xx_IRQ_L2_MASK;
io_be_setbit(&intr->ctrl, 11 - l2irq);
}
static void mpc52xx_extirq_ack(struct irq_data *d)
{
int irq;
int l2irq;
irq = irq_map[d->irq].hwirq;
l2irq = irq & MPC52xx_IRQ_L2_MASK;
io_be_setbit(&intr->ctrl, 27-l2irq);
}
static int mpc52xx_extirq_set_type(struct irq_data *d, unsigned int flow_type)
{
u32 ctrl_reg, type;
int irq;
int l2irq;
void *handler = handle_level_irq;
irq = irq_map[d->irq].hwirq;
l2irq = irq & MPC52xx_IRQ_L2_MASK;
pr_debug("%s: irq=%x. l2=%d flow_type=%d\n", __func__, irq, l2irq, flow_type);
switch (flow_type) {
case IRQF_TRIGGER_HIGH: type = 0; break;
case IRQF_TRIGGER_RISING: type = 1; handler = handle_edge_irq; break;
case IRQF_TRIGGER_FALLING: type = 2; handler = handle_edge_irq; break;
case IRQF_TRIGGER_LOW: type = 3; break;
default:
type = 0;
}
ctrl_reg = in_be32(&intr->ctrl);
ctrl_reg &= ~(0x3 << (22 - (l2irq * 2)));
ctrl_reg |= (type << (22 - (l2irq * 2)));
out_be32(&intr->ctrl, ctrl_reg);
__set_irq_handler_unlocked(d->irq, handler);
return 0;
}
static struct irq_chip mpc52xx_extirq_irqchip = {
.name = "MPC52xx External",
.irq_mask = mpc52xx_extirq_mask,
.irq_unmask = mpc52xx_extirq_unmask,
.irq_ack = mpc52xx_extirq_ack,
.irq_set_type = mpc52xx_extirq_set_type,
};
/*
* Main interrupt irq_chip
*/
static int mpc52xx_null_set_type(struct irq_data *d, unsigned int flow_type)
{
return 0; /* Do nothing so that the sense mask will get updated */
}
static void mpc52xx_main_mask(struct irq_data *d)
{
int irq;
int l2irq;
irq = irq_map[d->irq].hwirq;
l2irq = irq & MPC52xx_IRQ_L2_MASK;
io_be_setbit(&intr->main_mask, 16 - l2irq);
}
static void mpc52xx_main_unmask(struct irq_data *d)
{
int irq;
int l2irq;
irq = irq_map[d->irq].hwirq;
l2irq = irq & MPC52xx_IRQ_L2_MASK;
io_be_clrbit(&intr->main_mask, 16 - l2irq);
}
static struct irq_chip mpc52xx_main_irqchip = {
.name = "MPC52xx Main",
.irq_mask = mpc52xx_main_mask,
.irq_mask_ack = mpc52xx_main_mask,
.irq_unmask = mpc52xx_main_unmask,
.irq_set_type = mpc52xx_null_set_type,
};
/*
* Peripherals interrupt irq_chip
*/
static void mpc52xx_periph_mask(struct irq_data *d)
{
int irq;
int l2irq;
irq = irq_map[d->irq].hwirq;
l2irq = irq & MPC52xx_IRQ_L2_MASK;
io_be_setbit(&intr->per_mask, 31 - l2irq);
}
static void mpc52xx_periph_unmask(struct irq_data *d)
{
int irq;
int l2irq;
irq = irq_map[d->irq].hwirq;
l2irq = irq & MPC52xx_IRQ_L2_MASK;
io_be_clrbit(&
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