/*
* Copyright 2017, Nicholas Piggin, IBM Corporation
* Licensed under GPLv2.
*/
#define pr_fmt(fmt) "dt-cpu-ftrs: " fmt
#include <linux/export.h>
#include <linux/init.h>
#include <linux/jump_label.h>
#include <linux/memblock.h>
#include <linux/printk.h>
#include <linux/sched.h>
#include <linux/string.h>
#include <linux/threads.h>
#include <asm/cputable.h>
#include <asm/dt_cpu_ftrs.h>
#include <asm/mmu.h>
#include <asm/oprofile_impl.h>
#include <asm/prom.h>
#include <asm/setup.h>
/* Device-tree visible constants follow */
#define ISA_V2_07B 2070
#define ISA_V3_0B 3000
#define USABLE_PR (1U << 0)
#define USABLE_OS (1U << 1)
#define USABLE_HV (1U << 2)
#define HV_SUPPORT_HFSCR (1U << 0)
#define OS_SUPPORT_FSCR (1U << 0)
/* For parsing, we define all bits set as "NONE" case */
#define HV_SUPPORT_NONE 0xffffffffU
#define OS_SUPPORT_NONE 0xffffffffU
struct dt_cpu_feature {
const char *name;
uint32_t isa;
uint32_t usable_privilege;
uint32_t hv_support;
uint32_t os_support;
uint32_t hfscr_bit_nr;
uint32_t fscr_bit_nr;
uint32_t hwcap_bit_nr;
/* fdt parsing */
unsigned long node;
int enabled;
int disabled;
};
#define CPU_FTRS_BASE \
(CPU_FTR_USE_TB | \
CPU_FTR_LWSYNC | \
CPU_FTR_FPU_UNAVAILABLE |\
CPU_FTR_NODSISRALIGN |\
CPU_FTR_NOEXECUTE |\
CPU_FTR_COHERENT_ICACHE | \
CPU_FTR_STCX_CHECKS_ADDRESS |\
CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
CPU_FTR_DAWR | \
CPU_FTR_ARCH_206 |\
CPU_FTR_ARCH_207S)
#define MMU_FTRS_HASH_BASE (MMU_FTRS_POWER8)
#define COMMON_USER_BASE (PPC_FEATURE_32 | PPC_FEATURE_64 | \
PPC_FEATURE_ARCH_2_06 |\
PPC_FEATURE_ICACHE_SNOOP)
#define COMMON_USER2_BASE (PPC_FEATURE2_ARCH_2_07 | \
PPC_FEATURE2_ISEL)
/*
* Set up the base CPU
*/
extern void __flush_tlb_power8(unsigned int action);
extern void __flush_tlb_power9(unsigned int action);
extern long __machine_check_early_realmode_p8(struct pt_regs *regs);
extern long __machine_check_early_realmode_p9(struct pt_regs *regs);
static int hv_mode;
static struct {
u64 lpcr;
u64 hfscr;
u64 fscr;
} system_registers;
static void (*init_pmu_registers)(void);
static void cpufeatures_flush_tlb(void)
{
unsigned long rb;
unsigned int i, num_sets;
/*
* This is a temporary measure to keep equivalent TLB flush as the
* cputable based setup code.
*/
switch (PVR_VER(mfspr(SPRN_PVR))) {
case PVR_POWER8:
case PVR_POWER8E:
case PVR_POWER8NVL:
num_sets = POWER8_TLB_SETS;
break;
case PVR_POWER9:
num_sets = POWER9_TLB_SETS_HASH;
break;
default:
num_sets = 1;
pr_err("unknown CPU version for boot TLB flush\n");
break;
}
asm volatile("ptesync" : : : "memory");
rb = TLBIEL_INVAL_SET;
for (i = 0; i < num_sets; i++) {
asm volatile("tlbiel %0" : : "r" (rb));
rb += 1 << TLBIEL_INVAL_SET_SHIFT;
}
asm volatile("ptesync" : : : "memory");
}
static void __restore_cpu_cpufeatures(void)
{
/*
* LPCR is restored by the power on engine already. It can be changed
* after early init e.g., by radix enable, and we have no unified API
* for saving and restoring such SPRs.
*
* This ->restore hook should really be removed from idle and register
* restore moved directly into the idle restore code, because this code
* doesn't know how idle is implemented or what it needs restored here.
*
* The best we can do to accommodate secondary boot and idle restore
* for now is "or" LPCR with existing.
*/
mtspr(SPRN_LPCR, system_registers.lpcr | mfspr(SPRN_LPCR));
if (hv_mode) {
mtspr(SPRN_LPID, 0);
mtspr(SPRN_HFSCR, system_registers.hfscr);
}
mtspr(SPRN_FSCR, system_registers.fscr);
if (init_pmu_registers)
init_pmu_registers();
cpufeatures_flush_tlb();
}
static char dt_cpu_name[64];
static struct cpu_spec __initdata base_cpu_spec = {
.cpu_name = NULL,
.cpu_features = CPU_FTRS_BASE,
.cpu_user_features = COMMON_USER_BASE,
.cpu_user_features2 = COMMON_USER2_BASE,
.mmu_features = 0,
.icache_bsize = 32, /* minimum block size, fixed by */
.dcache_bsize = 32, /* cache info init. */
.num_pmcs = 0,
.pmc_type = PPC_PMC_DEFAULT,
.oprofile_cpu_type = NULL,
.oprofile_type = PPC_OPROFILE_INVALID,
.cpu_setup = NULL,
.cpu_restore = __restore_cpu_cpufeatures,
.flush_tlb = NULL,
.machine_check_early = NULL,
.platform = NULL,
};
static void __init cpufeatures_setup_cpu(void)
{
set_cur_cpu_spec(&base_cpu_spec);
cur_cpu_spec->pvr_mask = -1;
cur_cpu_spec->pvr_value = mfspr(SPRN_PVR);
/* Initialize the base environment -- clear FSCR/HFSCR. */
hv_mode = !!(mfmsr() &