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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Communication Processor Module v2.
*
* This file contains structures and information for the communication
* processor channels found in the dual port RAM or parameter RAM.
* All CPM control and status is available through the CPM2 internal
* memory map. See immap_cpm2.h for details.
*/
#ifdef __KERNEL__
#ifndef __CPM2__
#define __CPM2__
#include <asm/immap_cpm2.h>
#include <asm/cpm.h>
#include <sysdev/fsl_soc.h>
/* CPM Command register.
*/
#define CPM_CR_RST ((uint)0x80000000)
#define CPM_CR_PAGE ((uint)0x7c000000)
#define CPM_CR_SBLOCK ((uint)0x03e00000)
#define CPM_CR_FLG ((uint)0x00010000)
#define CPM_CR_MCN ((uint)0x00003fc0)
#define CPM_CR_OPCODE ((uint)0x0000000f)
/* Device sub-block and page codes.
*/
#define CPM_CR_SCC1_SBLOCK (0x04)
#define CPM_CR_SCC2_SBLOCK (0x05)
#define CPM_CR_SCC3_SBLOCK (0x06)
#define CPM_CR_SCC4_SBLOCK (0x07)
#define CPM_CR_SMC1_SBLOCK (0x08)
#define CPM_CR_SMC2_SBLOCK (0x09)
#define CPM_CR_SPI_SBLOCK (0x0a)
#define CPM_CR_I2C_SBLOCK (0x0b)
#define CPM_CR_TIMER_SBLOCK (0x0f)
#define CPM_CR_RAND_SBLOCK (0x0e)
#define CPM_CR_FCC1_SBLOCK (0x10)
#define CPM_CR_FCC2_SBLOCK (0x11)
#define CPM_CR_FCC3_SBLOCK (0x12)
#define CPM_CR_IDMA1_SBLOCK (0x14)
#define CPM_CR_IDMA2_SBLOCK (0x15)
#define CPM_CR_IDMA3_SBLOCK (0x16)
#define CPM_CR_IDMA4_SBLOCK (0x17)
#define CPM_CR_MCC1_SBLOCK (0x1c)
#define CPM_CR_FCC_SBLOCK(x) (x + 0x10)
#define CPM_CR_SCC1_PAGE (0x00)
#define CPM_CR_SCC2_PAGE (0x01)
#define CPM_CR_SCC3_PAGE (0x02)
#define CPM_CR_SCC4_PAGE (0x03)
#define CPM_CR_SMC1_PAGE (0x07)
#define CPM_CR_SMC2_PAGE (0x08)
#define CPM_CR_SPI_PAGE (0x09)
#define CPM_CR_I2C_PAGE (0x0a)
#define CPM_CR_TIMER_PAGE (0x0a)
#define CPM_CR_RAND_PAGE (0x0a)
#define CPM_CR_FCC1_PAGE (0x04)
#define CPM_CR_FCC2_PAGE (0x05)
#define CPM_CR_FCC3_PAGE (0x06)
#define CPM_CR_IDMA1_PAGE (0x07)
#define CPM_CR_IDMA2_PAGE (0x08)
#define CPM_CR_IDMA3_PAGE (0x09)
#define CPM_CR_IDMA4_PAGE (0x0a)
#define CPM_CR_MCC1_PAGE (0x07)
#define CPM_CR_MCC2_PAGE (0x08)
#define CPM_CR_FCC_PAGE(x) (x + 0x04)
/* CPM2-specific opcodes (see cpm.h for common opcodes)
*/
#define CPM_CR_START_IDMA ((ushort)0x0009)
#define mk_cr_cmd(PG, SBC, MCN, OP) \
((PG << 26) | (SBC << 21) | (MCN << 6) | OP)
/* The number of pages of host memory we allocate for CPM. This is
* done early in kernel initialization to get physically contiguous
* pages.
*/
#define NUM_CPM_HOST_PAGES 2
/* Export the base address of the communication processor registers
* and dual port ram.
*/
extern cpm_cpm2_t __iomem *cpmp; /* Pointer to comm processor */
#define cpm_dpalloc cpm_muram_alloc
#define cpm_dpfree cpm_muram_free
#define cpm_dpram_addr cpm_muram_addr
extern void cpm2_reset(void);
/* Baud rate generators.
*/
#define CPM_BRG_RST ((uint)0x00020000)
#define CPM_BRG_EN ((uint)0x00010000)
#define CPM_BRG_EXTC_INT ((uint)0x00000000)
#define CPM_BRG_EXTC_CLK3_9 ((uint)0x00004000)
#define CPM_BRG_EXTC_CLK5_15 ((uint)0x00008000)
#define CPM_BRG_ATB ((uint)0x00002000)
#define CPM_BRG_CD_MASK ((uint)0x00001ffe)
#define CPM_BRG_DIV16 ((uint)0x00000001)
#define CPM2_BRG_INT_CLK (get_brgfreq())
#define CPM2_BRG_UART_CLK (CPM2_BRG_INT_CLK/16)
extern void __cpm2_setbrg(uint brg, uint rate, uint clk, int div16, int src);
/* This function is used by UARTS, or anything else that uses a 16x
* oversampled clock.
*/
static inline void cpm_setbrg(uint brg, uint rate)
{
__cpm2_setbrg(brg, rate, CPM2_BRG_UART_CLK, 0, CPM_BRG_EXTC_INT);
}
/* This function is used to set high speed synchronous baud rate
* clocks.
*/
static inline void cpm2_fastbrg(uint brg, uint rate, int div16)
{
__cpm2_setbrg(brg, rate, CPM2_BRG_INT_CLK, div16, CPM_BRG_EXTC_INT);
}
/* Parameter RAM offsets from the base.
*/
#define PROFF_SCC1 ((uint)0x8000)
#define PROFF_SCC2 ((uint)0x8100)
#define PROFF_SCC3 ((uint)0x8200)
#define PROFF_SCC4 ((uint)0x8300)
#define PROFF_FCC1 ((uint)0x8400)
#define PROFF_FCC2 ((uint)0x8500)
#define PROFF_FCC3 ((uint)0x8600)
#define PROFF_MCC1 ((uint)0x8700)
#define PROFF_SMC1_BASE ((uint)0x87fc)
#define PROFF_IDMA1_BASE ((uint)0x87fe)
#define PROFF_MCC2 ((uint)0x8800)
#define PROFF_SMC2_BASE ((uint)0x88fc)
#define PROFF_IDMA2_BASE ((uint)0x88fe)
#define PROFF_SPI_BASE ((uint)0x89fc)
#define PROFF_IDMA3_BASE ((uint)0x89fe)
#define PROFF_TIMERS ((uint)0x8ae0)
#define PROFF_REVNUM ((uint)0x8af0)
#define PROFF_RAND ((uint)0x8af8)
#define PROFF_I2C_BASE ((uint)0x8afc)
#define PROFF_IDMA4_BASE ((uint)0x8afe)
#define PROFF_SCC_SIZE ((uint)0x100)
#define PROFF_FCC_SIZE ((uint)0x100)
#define PROFF_SMC_SIZE ((uint)64)
/* The SMCs are relocated to any of the first eight DPRAM pages.
* We will fix these at the first locations of DPRAM, until we
* get some microcode patches :-).
* The parameter ram space for the SMCs is fifty-some bytes, and
* they are required to start on a 64 byte boundary.
*/
#define PROFF_SMC1 (0)
#define PROFF_SMC2 (64)
/* Define enough so I can at least use the serial port as a UART.
*/
typedef struct smc_uart {
ushort smc_rbase; /* Rx Buffer descriptor base address */
ushort smc_tbase; /* Tx Buffer descriptor base address */
u_char smc_rfcr; /* Rx function code */
u_char smc_tfcr; /* Tx function code */
ushort smc_mrblr; /* Max receive buffer length */
uint smc_rstate; /* Internal */
uint smc_idp; /* Internal */
ushort smc_rbptr; /* Internal */
ushort smc_ibc; /* Internal */
uint smc_rxtmp; /* Internal */
uint smc_tstate; /* Internal */
uint smc_tdp; /* Internal */
ushort smc_tbptr; /* Internal */
ushort smc_tbc; /* Internal */
uint smc_txtmp; /* Internal */
ushort smc_maxidl; /* Maximum idle characters */
ushort smc_tmpidl; /* Temporary idle counter */
ushort smc_brklen; /* Last received break length */
ushort smc_brkec; /* rcv'd break condition counter */
ushort smc_brkcr; /* xmt break count register */
ushort smc_rmask; /* Temporary bit mask */
uint smc_stmp; /* SDMA Temp */
} smc_uart_t;
/* SMC uart mode register (Internal memory map).
*/
#define SMCMR_REN ((ushort)0x0001)
#define SMCMR_TEN ((ushort)0x0002)
#define SMCMR_DM ((ushort)0x000c)
#define SMCMR_SM_GCI ((ushort)0x0000)
#define SMCMR_SM_UART ((ushort)0x0020)
#define SMCMR_SM_TRANS ((ushort)0x0030)
#define SMCMR_SM_MASK ((ushort)0x0030)
#define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */
#define SMCMR_REVD SMCMR_PM_EVEN
#define SMCMR_PEN ((ushort)0x0200) /* Parity enable */
#define SMCMR_BS SMCMR_PEN
#define SMCMR_SL ((ushort)0x0400) /* Two stops, else one */
#define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */
#define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK)
/* SM
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