1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
|
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Derived from IRIX <sys/SN/SN0/hubio.h>, Revision 1.80.
*
* Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc.
* Copyright (C) 1999 by Ralf Baechle
*/
#ifndef _ASM_SGI_SN_SN0_HUBIO_H
#define _ASM_SGI_SN_SN0_HUBIO_H
/*
* Hub I/O interface registers
*
* All registers in this file are subject to change until Hub chip tapeout.
* In general, the longer software name should be used when available.
*/
/*
* Slightly friendlier names for some common registers.
* The hardware definitions follow.
*/
#define IIO_WIDGET IIO_WID /* Widget identification */
#define IIO_WIDGET_STAT IIO_WSTAT /* Widget status register */
#define IIO_WIDGET_CTRL IIO_WCR /* Widget control register */
#define IIO_WIDGET_TOUT IIO_WRTO /* Widget request timeout */
#define IIO_WIDGET_FLUSH IIO_WTFR /* Widget target flush */
#define IIO_PROTECT IIO_ILAPR /* IO interface protection */
#define IIO_PROTECT_OVRRD IIO_ILAPO /* IO protect override */
#define IIO_OUTWIDGET_ACCESS IIO_IOWA /* Outbound widget access */
#define IIO_INWIDGET_ACCESS IIO_IIWA /* Inbound widget access */
#define IIO_INDEV_ERR_MASK IIO_IIDEM /* Inbound device error mask */
#define IIO_LLP_CSR IIO_ILCSR /* LLP control and status */
#define IIO_LLP_LOG IIO_ILLR /* LLP log */
#define IIO_XTALKCC_TOUT IIO_IXCC /* Xtalk credit count timeout*/
#define IIO_XTALKTT_TOUT IIO_IXTT /* Xtalk tail timeout */
#define IIO_IO_ERR_CLR IIO_IECLR /* IO error clear */
#define IIO_BTE_CRB_CNT IIO_IBCN /* IO BTE CRB count */
#define IIO_LLP_CSR_IS_UP 0x00002000
#define IIO_LLP_CSR_LLP_STAT_MASK 0x00003000
#define IIO_LLP_CSR_LLP_STAT_SHFT 12
/* key to IIO_PROTECT_OVRRD */
#define IIO_PROTECT_OVRRD_KEY 0x53474972756c6573ull /* "SGIrules" */
/* BTE register names */
#define IIO_BTE_STAT_0 IIO_IBLS_0 /* Also BTE length/status 0 */
#define IIO_BTE_SRC_0 IIO_IBSA_0 /* Also BTE source address 0 */
#define IIO_BTE_DEST_0 IIO_IBDA_0 /* Also BTE dest. address 0 */
#define IIO_BTE_CTRL_0 IIO_IBCT_0 /* Also BTE control/terminate 0 */
#define IIO_BTE_NOTIFY_0 IIO_IBNA_0 /* Also BTE notification 0 */
#define IIO_BTE_INT_0 IIO_IBIA_0 /* Also BTE interrupt 0 */
#define IIO_BTE_OFF_0 0 /* Base offset from BTE 0 regs. */
#define IIO_BTE_OFF_1 IIO_IBLS_1 - IIO_IBLS_0 /* Offset from base to BTE 1 */
/* BTE register offsets from base */
#define BTEOFF_STAT 0
#define BTEOFF_SRC (IIO_BTE_SRC_0 - IIO_BTE_STAT_0)
#define BTEOFF_DEST (IIO_BTE_DEST_0 - IIO_BTE_STAT_0)
#define BTEOFF_CTRL (IIO_BTE_CTRL_0 - IIO_BTE_STAT_0)
#define BTEOFF_NOTIFY (IIO_BTE_NOTIFY_0 - IIO_BTE_STAT_0)
#define BTEOFF_INT (IIO_BTE_INT_0 - IIO_BTE_STAT_0)
/*
* The following definitions use the names defined in the IO interface
* document for ease of reference. When possible, software should
* generally use the longer but clearer names defined above.
*/
#define IIO_BASE 0x400000
#define IIO_BASE_BTE0 0x410000
#define IIO_BASE_BTE1 0x420000
#define IIO_BASE_PERF 0x430000
#define IIO_PERF_CNT 0x430008
#define IO_PERF_SETS 32
#define IIO_WID 0x400000 /* Widget identification */
#define IIO_WSTAT 0x400008 /* Widget status */
#define IIO_WCR 0x400020 /* Widget control */
#define IIO_WSTAT_ECRAZY (1ULL << 32) /* Hub gone crazy */
#define IIO_WSTAT_TXRETRY (1ULL << 9) /* Hub Tx Retry timeout */
#define IIO_WSTAT_TXRETRY_MASK (0x7F)
#define IIO_WSTAT_TXRETRY_SHFT (16)
#define IIO_WSTAT_TXRETRY_CNT(w) (((w) >> IIO_WSTAT_TXRETRY_SHFT) & \
IIO_WSTAT_TXRETRY_MASK)
#define IIO_ILAPR 0x400100 /* Local Access Protection */
#define IIO_ILAPO 0x400108 /* Protection override */
#define IIO_IOWA 0x400110 /* outbound widget access */
#define IIO_IIWA 0x400118 /* inbound widget access */
#define IIO_IIDEM 0x400120 /* Inbound Device Error Mask */
#define IIO_ILCSR 0x400128 /* LLP control and status */
#define IIO_ILLR 0x400130 /* LLP Log */
#define IIO_IIDSR 0x400138 /* Interrupt destination */
#define IIO_IIBUSERR 0x1400208 /* Reads here cause a bus error. */
/* IO Interrupt Destination Register */
#define IIO_IIDSR_SENT_SHIFT 28
#define IIO_IIDSR_SENT_MASK 0x10000000
#define IIO_IIDSR_ENB_SHIFT 24
#define IIO_IIDSR_ENB_MASK 0x01000000
#define IIO_IIDSR_NODE_SHIFT 8
#define IIO_IIDSR_NODE_MASK 0x0000ff00
#define IIO_IIDSR_LVL_SHIFT 0
#define IIO_IIDSR_LVL_MASK 0x0000003f
/* GFX Flow Control Node/Widget Register */
#define IIO_IGFX_0 0x400140 /* gfx node/widget register 0 */
#define IIO_IGFX_1 0x400148 /* gfx node/widget register 1 */
#define IIO_IGFX_W_NUM_BITS 4 /* size of widget num field */
#define IIO_IGFX_W_NUM_MASK ((1<<IIO_IGFX_W_NUM_BITS)-1)
#define IIO_IGFX_W_NUM_SHIFT 0
#define IIO_IGFX_N_NUM_BITS 9 /* size of node num field */
#define IIO_IGFX_N_NUM_MASK ((1<<IIO_IGFX_N_NUM_BITS)-1)
#define IIO_IGFX_N_NUM_SHIFT 4
#define IIO_IGFX_P_NUM_BITS 1 /* size of processor num field */
#define IIO_IGFX_P_NUM_MASK ((1<<IIO_IGFX_P_NUM_BITS)-1)
#define IIO_IGFX_P_NUM_SHIFT 16
#define IIO_IGFX_VLD_BITS 1 /* size of valid field */
#define IIO_IGFX_VLD_MASK ((1<<IIO_IGFX_VLD_BITS)-1)
#define IIO_IGFX_VLD_SHIFT 20
#define IIO_IGFX_INIT(widget, node, cpu, valid) (\
(((widget) & IIO_IGFX_W_NUM_MASK) << IIO_IGFX_W_NUM_SHIFT) | \
(((node) & IIO_IGFX_N_NUM_MASK) << IIO_IGFX_N_NUM_SHIFT) | \
(((cpu) & IIO_IGFX_P_NUM_MASK) << IIO_IGFX_P_NUM_SHIFT) | \
(((valid) & IIO_IGFX_VLD_MASK) << IIO_IGFX_VLD_SHIFT) )
/* Scratch registers (not all bits available) */
#define IIO_SCRATCH_REG0 0x400150
#define IIO_SCRATCH_REG1 0x400158
#define IIO_SCRATCH_MASK 0x0000000f00f11fff
#define IIO_SCRATCH_BIT0_0 0x0000000800000000
#define IIO_SCRATCH_BIT0_1 0x0000000400000000
#define IIO_SCRATCH_BIT0_2 0x0000000200000000
#define IIO_SCRATCH_BIT0_3 0x0000000100000000
#define IIO_SCRATCH_BIT0_4 0x0000000000800000
#define IIO_SCRATCH_BIT0_5 0x0000000000400000
#define IIO_SCRATCH_BIT0_6 0x0000000000200000
#define IIO_SCRATCH_BIT0_7 0x0000000000100000
#define IIO_SCRATCH_BIT0_8 0x0000000000010000
#define IIO_SCRATCH_BIT0_9 0x0000000000001000
#define IIO_SCRATCH_BIT0_R 0x0000000000000fff
/* IO Translation Table Entries */
#define IIO_NUM_ITTES 7 /* ITTEs numbered 0..6 */
/* Hw manuals number them 1..7! */
/*
* As a permanent workaround for a bug in the PI side of the hub, we've
* redefined big window 7 as small window 0.
*/
#define HUB_NUM_BIG_WINDOW IIO_NUM_ITTES - 1
/*
* Use the top big window as a surrogate for the first small window
*/
#define SWIN0_BIGWIN HUB_NUM_BIG_WINDOW
#define ILCSR_WARM_RESET 0x100
/*
* The IO LLP control status register and widget control register
*/
#ifndef __ASSEMBLY__
typedef union hubii_wid_u {
u64 wid_reg_value;
struct {
u64 wid_rsvd: 32, /* unused */
wid_rev_num: 4, /* revision number */
wid_part_num: 16, /* the widget type: hub=c101 */
wid_mfg_num: 11, /* Manufacturer id (IBM) */
wid_rsvd1: 1; /* Reserved */
} wid_fields_s;
} hubii_wid_t;
typedef union hubii_wcr_u {
u64 wcr_reg_value;
struct {
u64 wcr_rsvd: 41, /* unused */
wcr_e_thresh: 5, /* elasticity threshold */
wcr_dir_con: 1, /* widget direct connect */
wcr_f_bad_pkt: 1, /* Force bad llp pkt enable */
wcr_xbar_crd: 3, /* LLP crossbar credit */
wcr_rsvd1: 8, /* Reserved */
wcr_tag_mode: 1, /* Tag mode */
wcr_widget_id: 4; /* LLP crossbar credit */
} wcr_fields_s;
} hubii_wcr_t;
#define iwcr_dir_con wcr_fields_s.wcr_dir_con
typedef union hubii_wstat_u {
u64 reg_value;
struct {
u64 rsvd1: 31,
crazy: 1, /* Crazy bit */
rsvd2: 8,
llp_tx_cnt: 8, /* LLP Xmit retry counter */
rsvd3: 6,
tx_max_rtry: 1, /* LLP Retry Timeout Signal */
rsvd4: 2,
xt_tail_to: 1, /* Xtalk Tail Timeout */
xt_crd_to: 1, /* Xtalk Credit Timeout */
pending: 4; /* Pending Requests */
} wstat_fields_s;
} hubii_wstat_t;
typedef union hubii_ilcsr_u {
u64 icsr_reg_value;
struct {
u64 icsr_rsvd: 22, /* unused */
icsr_max_burst: 10, /* max burst */
icsr_rsvd4: 6, /* reserved */
icsr_max_retry: 10, /* max retry */
icsr_rsvd3: 2, /* reserved */
icsr_lnk_stat: 2, /* link status */
icsr_bm8: 1, /* Bit mode 8 */
icsr_llp_en: 1, /* LLP enable bit */
icsr_rsvd2: 1, /* reserver */
icsr_wrm_reset: 1, /* Warm reset bit */
icsr_rsvd1: 2, /* Data ready offset */
icsr_null_to: 6; /* Null timeout */
} icsr_fields_s;
} hubii_ilcsr_t;
typedef union hubii_iowa_u {
u64 iowa_reg_value;
struct {
u64 iowa_rsvd: 48, /* unused */
iowa_wxoac: 8, /* xtalk widget access bits */
iowa_rsvd1: 7
|