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/*
* XHCI HCD glue for Cavium Octeon III SOCs.
*
* Copyright (C) 2010-2017 Cavium Networks
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#include <linux/module.h>
#include <linux/device.h>
#include <linux/mutex.h>
#include <linux/delay.h>
#include <linux/of_platform.h>
#include <linux/io.h>
#include <asm/octeon/octeon.h>
/* USB Control Register */
union cvm_usbdrd_uctl_ctl {
uint64_t u64;
struct cvm_usbdrd_uctl_ctl_s {
/* 1 = BIST and set all USB RAMs to 0x0, 0 = BIST */
__BITFIELD_FIELD(uint64_t clear_bist:1,
/* 1 = Start BIST and cleared by hardware */
__BITFIELD_FIELD(uint64_t start_bist:1,
/* Reference clock select for SuperSpeed and HighSpeed PLLs:
* 0x0 = Both PLLs use DLMC_REF_CLK0 for reference clock
* 0x1 = Both PLLs use DLMC_REF_CLK1 for reference clock
* 0x2 = SuperSpeed PLL uses DLMC_REF_CLK0 for reference clock &
* HighSpeed PLL uses PLL_REF_CLK for reference clck
* 0x3 = SuperSpeed PLL uses DLMC_REF_CLK1 for reference clock &
* HighSpeed PLL uses PLL_REF_CLK for reference clck
*/
__BITFIELD_FIELD(uint64_t ref_clk_sel:2,
/* 1 = Spread-spectrum clock enable, 0 = SS clock disable */
__BITFIELD_FIELD(uint64_t ssc_en:1,
/* Spread-spectrum clock modulation range:
* 0x0 = -4980 ppm downspread
* 0x1 = -4492 ppm downspread
* 0x2 = -4003 ppm downspread
* 0x3 - 0x7 = Reserved
*/
__BITFIELD_FIELD(uint64_t ssc_range:3,
/* Enable non-standard oscillator frequencies:
* [55:53] = modules -1
* [52:47] = 2's complement push amount, 0 = Feature disabled
*/
__BITFIELD_FIELD(uint64_t ssc_ref_clk_sel:9,
/* Reference clock multiplier for non-standard frequencies:
* 0x19 = 100MHz on DLMC_REF_CLK* if REF_CLK_SEL = 0x0 or 0x1
* 0x28 = 125MHz on DLMC_REF_CLK* if REF_CLK_SEL = 0x0 or 0x1
* 0x32 = 50MHz on DLMC_REF_CLK* if REF_CLK_SEL = 0x0 or 0x1
* Other Values = Reserved
*/
__BITFIELD_FIELD(uint64_t mpll_multiplier:7,
/* Enable reference clock to prescaler for SuperSpeed functionality.
* Should always be set to "1"
*/
__BITFIELD_FIELD(uint64_t ref_ssp_en:1,
/* Divide the reference clock by 2 before entering the
* REF_CLK_FSEL divider:
* If REF_CLK_SEL = 0x0 or 0x1, then only 0x0 is legal
* If REF_CLK_SEL = 0x2 or 0x3, then:
* 0x1 = DLMC_REF_CLK* is 125MHz
* 0x0 = DLMC_REF_CLK* is another supported frequency
*/
__BITFIELD_FIELD(uint64_t ref_clk_div2:1,
/* Select reference clock freqnuency for both PLL blocks:
* 0x27 = REF_CLK_SEL is 0x0 or 0x1
* 0x07 = REF_CLK_SEL is 0x2 or 0x3
*/
__BITFIELD_FIELD(uint64_t ref_clk_fsel:6,
/* Reserved */
__BITFIELD_FIELD(uint64_t reserved_31_31:1,
/* Controller clock enable. */
__BITFIELD_FIELD(uint64_t h_clk_en:1,
/* Select bypass input to controller clock divider:
* 0x0 = Use divided coprocessor clock from H_CLKDIV
* 0x1 = Use clock from GPIO pins
*/
__BITFIELD_FIELD(uint64_t h_clk_byp_sel:1,
/* Reset controller clock divider. */
__BITFIELD_FIELD(uint64_t h_clkdiv_rst:1,
/* Reserved */
__BITFIELD_FIELD(uint64_t reserved_27_27:1,
/* Clock divider select:
* 0x0 = divide by 1
* 0x1 = divide by 2
* 0x2 = divide by 4
* 0x3 = divide by 6
* 0x4 = divide by 8
* 0x5 = divide by 16
* 0x6 = divide by 24
* 0x7 = divide by 32
*/
__BITFIELD_FIELD(uint64_t h_clkdiv_sel:3,
/* Reserved */
__BITFIELD_FIELD(uint64_t reserved_22_23:2,
/* USB3 port permanently attached: 0x0 = No, 0x1 = Yes */
__BITFIELD_FIELD(uint64_t usb3_port_perm_attach:1,
/* USB2 port permanently attached: 0x0 = No, 0x1 = Yes */
__BITFIELD_FIELD(uint64_t usb2_port_perm_attach:1,
/* Reserved */
__BITFIELD_FIELD(uint64_t reserved_19_19:1,
/* Disable SuperSpeed PHY: 0x0 = No, 0x1 = Yes */
__BITFIELD_FIELD(uint64_t usb3_port_disable:1,
/* Reserved */
__BITFIELD_FIELD(uint64_t reserved_17_17:1,
/* Disable HighSpeed PHY: 0x0 = No, 0x1 = Yes */
__BITFIELD_FIELD(uint64_t usb2_port_disable:1,
/* Reserved */
__BITFIELD_FIELD(uint64_t reserved_15_15:1,
/* Enable PHY SuperSpeed block power: 0x0 = No, 0x1 = Yes */
__BITFIELD_FIELD(uint64_t ss_power_en:1,
/* Reserved */
__BITFIELD_FIELD(uint64_t reserved_13_13:1,
/* Enable PHY HighSpeed block power: 0x0 = No, 0x1 = Yes */
__BITFIELD_FIELD(uint64_t hs_power_en:1,
/* Reserved */
__BITFIELD_FIELD(uint64_t reserved_5_11:7,
/* Enable USB UCTL interface clock: 0xx = No, 0x1 = Yes */
__BITFIELD_FIELD(uint64_t csclk_en:1,
/* Controller mode: 0x0 = Host, 0x1 = Device */
__BITFIELD_FIELD(uint64_t drd_mode:1,
/* PHY reset */
__BITFIELD_FIELD(uint64_t uphy_rst:1,
/* Software reset UAHC */
__BITFIELD_FIELD(uint64_t uahc_rst:1,
/* Software resets UCTL */
__BITFIELD_FIELD(uint64_t uctl_rst:1,
;)))))))))))))))))))))))))))))))))
} s;
};
/* UAHC Configuration Register */
union cvm_usbdrd_uctl_host_cfg {
uint64_t u64;
struct cvm_usbdrd_uctl_host_cfg_s {
/* Reserved */
__BITFIELD_FIELD(uint64_t reserved_60_63:4,
/* Indicates minimum value of all received BELT values */
__BITFIELD_FIELD(uint64_t host_current_belt:12,
/* Reserved */
__BITFIELD_FIELD(uint64_t reserved_38_47:10,
/* HS jitter adjustment */
__BITFIELD_FIELD(uint64_t fla:6,
/* Reserved */
__BITFIELD_FIELD(uint64_t reserved_29_31:3,
/* Bus-master enable: 0x0 = Disabled (stall DMAs), 0x1 = enabled */
__BITFIELD_FIELD(uint64_t bme:1,
/* Overcurrent protection enable: 0x0 = unavailable, 0x1 = available */
__BITFIELD_FIELD(uint64_t oci_en:1,
/* Overcurrent sene selection:
* 0x0 = Overcurrent indication from off-chip is active-low
* 0x1 = Overcurrent indication from off-chip is active-high
*/
__BITFIELD_FIELD(uint64_t oci_active_high_en:1,
/* Port power control enable: 0x0 = unavailable, 0x1 = available */
__BITFIELD_FIELD(uint64_t ppc_en:1,
/* Port power control sense selection:
* 0x0 = Port power to off-chip is active-low
* 0x1 = Port power to off-chip is active-high
*/
__BITFIELD_FIELD(uint64_t ppc_active_high_en:1,
/* Reserved */
__BITFIELD_FIELD(uint64_t reserved_0_23:24,
;)))))))))))
} s;
};
/* UCTL Shim Features Register */
union cvm_usbdrd_uctl_shim_cfg {
uint64_t u64;
struct cvm_usbdrd_uctl_shim_cfg_s {
/* Out-of-bound UAHC register access: 0 = read, 1 = write */
__BITFIELD_FIELD(uint64_t xs_ncb_oob_wrn:1,
/* Reserved */
__BITFIELD_FIELD(uint64_t reserved_60_62:3,
/* SRCID error log for out-of-bound UAHC register access:
* [59:58] = chipID
* [57] = Request source: 0 = core, 1 = NCB-device
* [56:51] = Core/NCB-device number, [56] always 0 for NCB devices
* [50:48] = SubID
*/
__BITFIELD_FIELD(uint64_t xs_ncb_oob_osrc:12,
/* Error log for bad UAHC DMA access: 0 = Read log, 1 = Write log */
__BITFIELD_FIELD(uint64_t xm_bad_dma_wrn:1,
/* Reserved */
__BITFIELD_FIELD(uint64_t reserved_44_46:3,
/* Encoded error type for bad UAHC DMA */
__BITFIELD_FIELD(uint64_t xm_bad_dma_type:4,
/* Reserved */
__BITFIELD_FIELD(uint64_t reserved_13_39:27,
/* Select the IOI read command used by DMA accesses */
__BITFIELD_FIELD(uint64_t dma_read_cmd:1,
/* Reserved */
__BITFIELD_FIELD(uint64_t reserved_10_11:2,
/* Select endian format for DMA accesses to the L2c:
* 0x0 = Little endian
*` 0x1 = Big endian
* 0x2 = Reserved
* 0x3 = Reserved
*/
__BITFIELD_FIELD(uint64_t dma_endian_mode:2,
/* Reserved */
__BITFIELD_FIELD(uint64_t reserved_2_7:6,
/* Select endian format for IOI CSR access to UAHC:
* 0x0 = Little endian
*` 0x1 = Big endian
* 0x2 = Reserved
* 0x3 = Reserved
*/
__BITFIELD_FIELD(uint64_t csr_endian_mode:2,
;))))))))))))
} s;
};
#define OCTEON_H_CLKDIV_SEL 8
#define OCTEON_MIN_H_CLK_RATE 150000000
#define OCTEON_MAX_H_CLK_RATE 300000000
static DEFINE_MUTEX(dwc3_octeon_clocks_mutex);
static uint8_t clk_div[OCTEON_H_CLKDIV_SEL] = {1, 2, 4, 6, 8, 16, 24, 32};
static int dwc3_octeon_config_power(struct device *dev, u64 base)
{
#define UCTL_HOST_CFG 0xe0
union cvm_usbdrd_uctl_host_cfg uctl_host_cfg;
union cvmx_gpio_bit_cfgx gpio_bit;
uint32_t gpio_pwr[3];
int gpio, len, power_active_low;
struct device_node *node = dev->of_node;
int index = (base >> 24) & 1;
if (of_find_property(node, "power", &len) != NULL) {
if (len == 12) {
of_property_read_u32_array(node, "power", gpio_pwr, 3);
power_active_low = gpio_pwr[2] & 0x01;
gpio = gpio_pwr[1];
} else if (len == 8) {
of_property_read_u32_array(node, "power", gpio_pwr, 2);
power_active_low = 0;
gpio = gpio_pwr[1];
} else {
dev_err(dev, "dwc3 controller clock init failure.\n");
return -EINVAL;
}
if ((OCTEON_IS_MODEL(OCTEON_CN73XX) ||
OCTEON_IS_MODEL(OCTEON_CNF75XX))
&& gpio <= 31) {
gpio_bit.u64 = cvmx_read_csr(CVMX_GPIO_BIT_CFGX(gpio));
gpio_bit.s.tx_oe = 1;
gpio_bit.cn73xx.output_sel = (index == 0 ? 0x14 : 0x15);
cvmx_write_csr(CVMX_GPIO_BIT_CFGX(gpio), gpio_bit.u64);
} else if (gpio <= 15) {
gpio_bit.u64 = cvmx_read_csr(CVMX_GPIO_BIT_CFGX(gpio));
gpio_bit.s.tx_oe = 1;
gpio_bit.cn70xx.output_sel = (index == 0 ? 0x14 : 0x19);
cvmx_write_csr(CVMX_GPIO_BIT_CFGX(gpio), gpio_bit.u64);
} else {
gpio_bit.u64 = cvmx_read_csr(CVMX_GPIO_XBIT_CFGX(gpio
|