/*
* Exception handling for Microblaze
*
* Rewriten interrupt handling
*
* Copyright (C) 2008-2009 Michal Simek <monstr@monstr.eu>
* Copyright (C) 2008-2009 PetaLogix
*
* uClinux customisation (C) 2005 John Williams
*
* MMU code derived from arch/ppc/kernel/head_4xx.S:
* Copyright (C) 1995-1996 Gary Thomas <gdt@linuxppc.org>
* Initial PowerPC version.
* Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
* Rewritten for PReP
* Copyright (C) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
* Low-level exception handers, MMU support, and rewrite.
* Copyright (C) 1997 Dan Malek <dmalek@jlc.net>
* PowerPC 8xx modifications.
* Copyright (C) 1998-1999 TiVo, Inc.
* PowerPC 403GCX modifications.
* Copyright (C) 1999 Grant Erickson <grant@lcse.umn.edu>
* PowerPC 403GCX/405GP modifications.
* Copyright 2000 MontaVista Software Inc.
* PPC405 modifications
* PowerPC 403GCX/405GP modifications.
* Author: MontaVista Software, Inc.
* frank_rowand@mvista.com or source@mvista.com
* debbie_chu@mvista.com
*
* Original code
* Copyright (C) 2004 Xilinx, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
/*
* Here are the handlers which don't require enabling translation
* and calling other kernel code thus we can keep their design very simple
* and do all processing in real mode. All what they need is a valid current
* (that is an issue for the CONFIG_REGISTER_TASK_PTR case)
* This handlers use r3,r4,r5,r6 and optionally r[current] to work therefore
* these registers are saved/restored
* The handlers which require translation are in entry.S --KAA
*
* Microblaze HW Exception Handler
* - Non self-modifying exception handler for the following exception conditions
* - Unalignment
* - Instruction bus error
* - Data bus error
* - Illegal instruction opcode
* - Divide-by-zero
*
* - Privileged instruction exception (MMU)
* - Data storage exception (MMU)
* - Instruction storage exception (MMU)
* - Data TLB miss exception (MMU)
* - Instruction TLB miss exception (MMU)
*
* Note we disable interrupts during exception handling, otherwise we will
* possibly get multiple re-entrancy if interrupt handles themselves cause
* exceptions. JW
*/
#include <asm/exceptions.h>
#include <asm/unistd.h>
#include <asm/page.h>
#include <asm/entry.h>
#include <asm/current.h>
#include <linux/linkage.h>
#include <asm/mmu.h>
#include <asm/pgtable.h>
#include <asm/signal.h>
#include <asm/asm-offsets.h>
#undef DEBUG
/* Helpful Macros */
#define NUM_TO_REG(num) r ## num
#ifdef CONFIG_MMU
#define RESTORE_STATE \
lwi r5, r1, 0; \
mts rmsr, r5; \
nop; \
lwi r3, r1, PT_R3; \
lwi r4, r1, PT_R4; \
lwi r5, r1, PT_R5; \
lwi r6, r1, PT_R6; \
lwi r11, r1, PT_R11; \
lwi r31, r1, PT_R31; \
lwi r1, r1, PT_R1;
#endif /* CONFIG_MMU */
#define LWREG_NOP \
bri ex_handler_unhandled; \
nop;
#define SWREG_NOP \
bri ex_handler_unhandled; \
nop;
/* FIXME this is weird - for noMMU kernel is not possible to use brid
* instruction which can shorten executed time
*/
/* r3 is the source */
#define R3_TO_LWREG_V(regnum) \
swi r3, r1, 4 * regnum; \
bri ex_handler_done;
/* r3 is the source */
#define R3_TO_LWREG(regnum) \
or NUM_TO_REG (regnum), r0, r3; \
bri ex_handler_done;
/* r3 is the target */
#define SWREG_TO_R3_V(regnum) \
lwi r3, r1, 4 * regnum; \
bri ex_sw_tail;
/* r3 is the target */
#define SWREG_TO_R3(regnum) \
or r3, r0, NUM_TO_REG (regnum); \
bri ex_sw_tail;
#ifdef CONFIG_MMU
#define R3_TO_LWREG_VM_V(regnum) \
brid ex_lw_end_vm; \
swi r3, r7, 4 * regnum;
#define R3_TO_LWREG_VM(regnum) \
brid ex_lw_end_vm; \
or NUM_TO_REG (regnum), r0, r3;
#define SWREG_TO_R3_VM_V(regnum) \
brid ex_sw_tail_vm; \
lwi r3, r7, 4 * regnum;
#define SWREG_TO_R3_VM(regnum) \
brid ex_sw_tail_vm; \
or r3, r0, NUM_TO_REG (regnum);
/* Shift right instruction depending on available configuration */
#if CONFIG_XILINX_MICROBLAZE0_USE_BARREL > 0
#define BSRLI(rD, rA, imm) \
bsrli rD, rA, imm
#else
#define BSRLI(rD, rA, imm) BSRLI ## imm (rD, rA)
/* Only the used shift constants defined here - add more if needed */
#define BSRLI2(rD, rA) \
srl rD, rA; /* << 1 */ \
srl rD, rD; /* << 2 */
#define BSRLI10(rD, rA) \
srl rD, rA; /* << 1 */ \
srl rD, rD; /* << 2 */ \
srl rD, rD; /* << 3 */ \
srl rD, rD; /* << 4 */ \
srl rD, rD; /* << 5 */ \
srl rD, rD; /* << 6 */ \
srl rD, rD; /* << 7 */ \<