/* * Set up the interrupt priorities * * Copyright 2004-2009 Analog Devices Inc. * 2003 Bas Vermeulen <bas@buyways.nl> * 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca> * 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca> * 1999 D. Jeff Dionne <jeff@uclinux.org> * 1996 Roman Zippel * * Licensed under the GPL-2 */#include<linux/module.h>#include<linux/kernel_stat.h>#include<linux/seq_file.h>#include<linux/irq.h>#ifdef CONFIG_IPIPE#include<linux/ipipe.h>#endif#ifdef CONFIG_KGDB#include<linux/kgdb.h>#endif#include<asm/traps.h>#include<asm/blackfin.h>#include<asm/gpio.h>#include<asm/irq_handler.h>#include<asm/dpmc.h>#include<asm/bfin5xx_spi.h>#include<asm/bfin_sport.h>#include<asm/bfin_can.h>#define SIC_SYSIRQ(irq) (irq - (IRQ_CORETMR + 1))#ifdef BF537_FAMILY# define BF537_GENERIC_ERROR_INT_DEMUX# define SPI_ERR_MASK (BIT_STAT_TXCOL | BIT_STAT_RBSY | BIT_STAT_MODF | BIT_STAT_TXE) /* SPI_STAT */# define SPORT_ERR_MASK (ROVF | RUVF | TOVF | TUVF) /* SPORT_STAT */# define PPI_ERR_MASK (0xFFFF & ~FLD) /* PPI_STATUS */# define EMAC_ERR_MASK (PHYINT | MMCINT | RXFSINT | TXFSINT | WAKEDET | RXDMAERR | TXDMAERR | STMDONE) /* EMAC_SYSTAT */# define UART_ERR_MASK (0x6) /* UART_IIR */# define CAN_ERR_MASK (EWTIF | EWRIF | EPIF | BOIF | WUIF | UIAIF | AAIF | RMLIF | UCEIF | EXTIF | ADIF) /* CAN_GIF */#else# undef BF537_GENERIC_ERROR_INT_DEMUX#endif/* * NOTES: * - we have separated the physical Hardware interrupt from the * levels that the LINUX kernel sees (see the description in irq.h) * - */#ifndef CONFIG_SMP/* Initialize this to an actual value to force it into the .data * section so that we know it is properly initialized at entry into * the kernel but before bss is initialized to zero (which is where * it would live otherwise). The 0x1f magic represents the IRQs we * cannot actually mask out in hardware. */unsignedlongbfin_irq_flags=0x1f;EXPORT_SYMBOL(bfin_irq_flags);#endif/* The number of spurious interrupts */atomic_tnum_spurious;#ifdef CONFIG_PMunsignedlongbfin_sic_iwr[3];/* Up to 3 SIC_IWRx registers */unsignedvr_wakeup;#endifstructivgx{/* irq number for request_irq, available in mach-bf5xx/irq.h */unsignedintirqno;/* corresponding bit in the SIC_ISR register */unsignedintisrflag;}ivg_table[NR_PERI_INTS];structivg_slice{/* position of first