/* * Set up the interrupt priorities * * Copyright 2004-2009 Analog Devices Inc. * 2003 Bas Vermeulen <bas@buyways.nl> * 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca> * 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca> * 1999 D. Jeff Dionne <jeff@uclinux.org> * 1996 Roman Zippel * * Licensed under the GPL-2 */#include<linux/module.h>#include<linux/kernel_stat.h>#include<linux/seq_file.h>#include<linux/irq.h>#include<linux/sched.h>#include<linux/syscore_ops.h>#include<asm/delay.h>#ifdef CONFIG_IPIPE#include<linux/ipipe.h>#endif#include<asm/traps.h>#include<asm/blackfin.h>#include<asm/gpio.h>#include<asm/irq_handler.h>#include<asm/dpmc.h>#include<asm/traps.h>/* * NOTES: * - we have separated the physical Hardware interrupt from the * levels that the LINUX kernel sees (see the description in irq.h) * - */#ifndef CONFIG_SMP/* Initialize this to an actual value to force it into the .data * section so that we know it is properly initialized at entry into * the kernel but before bss is initialized to zero (which is where * it would live otherwise). The 0x1f magic represents the IRQs we * cannot actually mask out in hardware. */unsignedlongbfin_irq_flags=0x1f;EXPORT_SYMBOL(bfin_irq_flags);#endif#ifdef CONFIG_PMunsignedlongbfin_sic_iwr[3];/* Up to 3 SIC_IWRx registers */unsignedvr_wakeup;#endif#ifndef SEC_GCTLstaticstructivgx{/* irq number for request_irq, available in mach-bf5xx/irq.h */unsignedintirqno;/* corresponding bit in the SIC_ISR register */unsignedintisrflag;}ivg_table[NR_PERI_INTS];staticstructivg_slice{/* position of first irq in ivg_table for given ivg */structivgx*ifirst;structivgx*istop;}ivg7_13[IVG13-IVG7+1];/* * Search SIC_IAR and fill tables with the irqvalues * and their positions in the SIC_ISR register. */staticvoid__initsearch_IAR(void){unsignedivg,irq_pos=0;for(ivg=0;ivg<=IVG13-IVG7;ivg++){intirqN;ivg7_13[ivg].istop=ivg7_13[ivg].ifirst=&ivg_table[irq_pos];for(irqN=0;irqN<NR_PERI_INTS;irqN+=4){