/*
* Copyright (c) 2017 MediaTek Inc.
* Author: Ming Huang <ming.huang@mediatek.com>
* Sean Wang <sean.wang@mediatek.com>
*
* SPDX-License-Identifier: (GPL-2.0 OR MIT)
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/mt7622-clk.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/power/mt7622-power.h>
#include <dt-bindings/reset/mt7622-reset.h>
#include <dt-bindings/thermal/thermal.h>
/ {
compatible = "mediatek,mt7622";
interrupt-parent = <&sysirq>;
#address-cells = <2>;
#size-cells = <2>;
cpu_opp_table: opp-table {
compatible = "operating-points-v2";
opp-shared;
opp-300000000 {
opp-hz = /bits/ 64 <30000000>;
opp-microvolt = <950000>;
};
opp-437500000 {
opp-hz = /bits/ 64 <437500000>;
opp-microvolt = <1000000>;
};
opp-600000000 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <1050000>;
};
opp-812500000 {
opp-hz = /bits/ 64 <812500000>;
opp-microvolt = <1100000>;
};
opp-1025000000 {
opp-hz = /bits/ 64 <1025000000>;
opp-microvolt = <1150000>;
};
opp-1137500000 {
opp-hz = /bits/ 64 <1137500000>;
opp-microvolt = <1200000>;
};
opp-1262500000 {
opp-hz = /bits/ 64 <1262500000>;
opp-microvolt = <1250000>;
};
opp-1350000000 {
opp-hz = /bits/ 64 <1350000000>;
opp-microvolt = <1310000>;
};
};
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x0>;
clocks = <&infracfg CLK_INFRA_MUX1_SEL>,
<&apmixedsys CLK_APMIXED_MAIN_CORE_EN>;
clock-names = "cpu", "intermediate";
operating-points-v2 = <&cpu_opp_table>;
#cooling-cells = <2>;
enable-method = "psci";
clock-frequency = <1300000000>;
cci-control-port = <&cci_control2>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x1>;
clocks = <&infracfg CLK_INFRA_MUX1_SEL>,
<&apmixedsys CLK_APMIXED_MAIN_CORE_EN>;
clock-names = "cpu", "intermediate";
operating-points-v2 = <&cpu_opp_table>;
#cooling-cells = <2>;
enable-method = "psci";
clock-frequency = <1300000000>;
cci-control-port = <&cci_control2>;
};
};
pwrap_clk: dummy40m {
compatible = "fixed-clock";
clock-frequency = <40000000>;
#clock-cells = <0>;
};
clk25m: oscillator {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
clock-output-names = "clkxtal";
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 9 IRQ_TYPE_LEVEL_LOW>;
interrupt-affinity = <&cpu0>, <&cpu1>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
/* 192 KiB reserved for ARM Trusted Firmware (BL31) */
secmon_reserved: secmon@43000000 {
reg = <0 0x43000000 0 0x30000>;
no-map;
};
};
thermal-zones {
cpu_thermal: cpu-thermal {
polling-delay-passive = <1000>;
polling-delay = <1000>;
thermal-sensors = <&thermal 0>;
trips {
cpu_passive: cpu-passive {
temperature = <47000>;
hysteresis = <2000>;
type = "passive";
};
cpu_active: cpu-active {
temperature = <67000>;
hysteresis = <2000>;
type = "active";
};
cpu_hot: cpu-hot {
temperature = <87000>;
hysteresis = <2000>;
type = "hot";
};
cpu-crit {
temperature = <107000>;
hysteresis = <2000>