/*
* Copyright (c) 2017 MediaTek Inc.
* Author: YT Shen <yt.shen@mediatek.com>
*
* SPDX-License-Identifier: (GPL-2.0 OR MIT)
*/
#include <dt-bindings/clock/mt2712-clk.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/memory/mt2712-larb-port.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/power/mt2712-power.h>
#include "mt2712-pinfunc.h"
/ {
compatible = "mediatek,mt2712";
interrupt-parent = <&sysirq>;
#address-cells = <2>;
#size-cells = <2>;
cluster0_opp: opp_table0 {
compatible = "operating-points-v2";
opp-shared;
opp00 {
opp-hz = /bits/ 64 <598000000>;
opp-microvolt = <1000000>;
};
opp01 {
opp-hz = /bits/ 64 <702000000>;
opp-microvolt = <1000000>;
};
opp02 {
opp-hz = /bits/ 64 <793000000>;
opp-microvolt = <1000000>;
};
};
cluster1_opp: opp_table1 {
compatible = "operating-points-v2";
opp-shared;
opp00 {
opp-hz = /bits/ 64 <598000000>;
opp-microvolt = <1000000>;
};
opp01 {
opp-hz = /bits/ 64 <702000000>;
opp-microvolt = <1000000>;
};
opp02 {
opp-hz = /bits/ 64 <793000000>;
opp-microvolt = <1000000>;
};
opp03 {
opp-hz = /bits/ 64 <897000000>;
opp-microvolt = <1000000>;
};
opp04 {
opp-hz = /bits/ 64 <1001000000>;
opp-microvolt = <1000000>;
};
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu-map {
cluster0 {
core0 {
cpu = <&cpu0>;
};
core1 {
cpu = <&cpu1>;
};
};
cluster1 {
core0 {
cpu = <&cpu2>;
};
};
};
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a35";
reg = <0x000>;
clocks = <&mcucfg CLK_MCU_MP0_SEL>,
<&topckgen CLK_TOP_F_MP0_PLL1>;
clock-names = "cpu", "intermediate";
proc-supply = <&cpus_fixed_vproc0>;
operating-points-v2 = <&cluster0_opp>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a35";
reg = <0x001>;
enable-method = "psci";
clocks = <&mcucfg CLK_MCU_MP0_SEL>,
<&topckgen CLK_TOP_F_MP0_PLL1>;
clock-names = "cpu", "intermediate";
proc-supply = <&cpus_fixed_vproc0>;
operating-points-v2 = <&cluster0_opp>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
cpu2: cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x200>;
enable-method = "psci";
clocks = <&mcucfg CLK_MCU_MP2_SEL>,
<&topckgen CLK_TOP_F_BIG_PLL1>;
clock-names = "cpu", "intermediate";
proc-supply = <&cpus_fixed_vproc1>;
operating-points-v2 = <&cluster1_opp>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
idle-states {
entry-method = "psci";
CPU_SLEEP_0: cpu-sleep-0 {
compatible = "arm,idle-state";
local-timer-stop;
entry-latency-us = <100>;
exit-latency-us = <80>;
min-residency-us = <2000>;
arm,psci-suspend-param = <0x0010000>;
};
CLUSTER_SLEEP_0: cluster-sleep-0 {
compatible = "arm,idle-state";
local-timer-stop;
entry-latency-us = <350>;
exit-latency-us = <80>;
min-residency-us = <3000>;
arm,psci-suspend-param = <0x1010000>;
};
};
};