summaryrefslogtreecommitdiffstats
path: root/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
blob: 755b4ad1518467247894b7890a25f11f41db3049 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
 */

#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/meson-a1-gpio.h>

/ {
	compatible = "amlogic,a1";

	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a35";
			reg = <0x0 0x0>;
			enable-method = "psci";
			next-level-cache = <&l2>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a35";
			reg = <0x0 0x1>;
			enable-method = "psci";
			next-level-cache = <&l2>;
		};

		l2: l2-cache0 {
			compatible = "cache";
		};
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		linux,cma {
			compatible = "shared-dma-pool";
			reusable;
			size = <0x0 0x800000>;
			alignment = <0x0 0x400000>;
			linux,cma-default;
		};
	};

	sm: secure-monitor {
		compatible = "amlogic,meson-gxbb-sm";

		pwrc: power-controller {
			compatible = "amlogic,meson-a1-pwrc";
			#power-domain-cells = <1>;
			status = "okay";
		};
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		apb: bus@fe000000 {
			compatible = "simple-bus";
			reg = <0x0 0xfe000000 0x0 0x1000000>;
			#address-cells = <2>;
			#size-cells = <2>;
			ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x1000000>;


			reset: reset-controller@0 {
				compatible = "amlogic,meson-a1-reset";
				reg = <0x0 0x0 0x0 0x8c>;
				#reset-cells = <1>;
			};

			periphs_pinctrl: pinctrl@0400 {
				compatible = "amlogic,meson-a1-periphs-pinctrl";
				#address-cells = <2>;
				#size-cells = <2>;
				ranges;

				gpio: bank@0400 {
					reg = <0x0 0x0400 0x0 0x003c>,
					      <0x0 0x0480 0x0 0x0118>;
					reg-names = "mux", "gpio";
					gpio-controller;
					#gpio-cells = <2>;
					gpio-ranges = <&periphs_pinctrl 0 0 62>;
				};

			};

			uart_AO: serial@1c00 {
				compatible = "amlogic,meson-gx-uart",
					     "amlogic,meson-ao-uart";
				reg = <0x0 0x1c00 0x0 0x18>;
				interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
				clocks = <&xtal>, <&xtal>, <&xtal>;
				clock-names = "xtal", "pclk", "baud";
				status = "disabled";
			};

			uart_AO_B: serial@2000 {
				compatible = "amlogic,meson-gx-uart",
					     "amlogic,meson-ao-uart";
				reg = <0x0 0x2000 0x0 0x18>;
				interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
				clocks = <&xtal>, <&xtal>, <&xtal>;
				clock-names = "xtal", "pclk", "baud";
				status = "disabled";
			};
		};

		gic: interrupt-controller@ff901000 {
			compatible = "arm,gic-400";
			reg = <0x0 0xff901000 0x0 0x1000>,
			      <0x0 0xff902000 0x0 0x2000>,
			      <0x0 0xff904000 0x0 0x2000>,
			      <0x0 0xff906000 0x0 0x2000>;
			interrupt-controller;
			interrupts = <GIC_PPI 9
				(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
			#interrupt-cells = <3>;
			#address-cells = <0>;
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13
			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14
			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11
			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10
			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
	};

	xtal: xtal-clk {
		compatible = "fixed-clock";
		clock-frequency = <24000000>;
		clock-output-names = "xtal";
		#clock-cells = <0>;
	};
};