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// SPDX-License-Identifier: GPL-2.0-only
/*
* L220/L310 cache controller support
*
* Copyright (C) 2016 ARM Limited
*/
#include <linux/errno.h>
#include <linux/hrtimer.h>
#include <linux/io.h>
#include <linux/list.h>
#include <linux/perf_event.h>
#include <linux/printk.h>
#include <linux/slab.h>
#include <linux/types.h>
#include <asm/hardware/cache-l2x0.h>
#define PMU_NR_COUNTERS 2
static void __iomem *l2x0_base;
static struct pmu *l2x0_pmu;
static cpumask_t pmu_cpu;
static const char *l2x0_name;
static ktime_t l2x0_pmu_poll_period;
static struct hrtimer l2x0_pmu_hrtimer;
/*
* The L220/PL310 PMU has two equivalent counters, Counter1 and Counter0.
* Registers controlling these are laid out in pairs, in descending order, i.e.
* the register for Counter1 comes first, followed by the register for
* Counter0.
* We ensure that idx 0 -> Counter0, and idx1 -> Counter1.
*/
static struct perf_event *events[PMU_NR_COUNTERS];
/* Find an unused counter */
static int l2x0_pmu_find_idx(void)
{
int i;
for (i = 0; i < PMU_NR_COUNTERS; i++) {
if (!events[i])
return i;
}
return -1;
}
/* How many counters are allocated? */
static int l2x0_pmu_num_active_counters(void)
{
int i, cnt = 0;
for (i = 0; i < PMU_NR_COUNTERS; i++) {
if (events[i])
cnt++;
}
return cnt;
}
static void l2x0_pmu_counter_config_write(int idx, u32 val)
{
writel_relaxed(val, l2x0_base + L2X0_EVENT_CNT0_CFG - 4 * idx);
}
static u32 l2x0_pmu_counter_read(int idx)
{
return readl_relaxed(l2x0_base + L2X0_EVENT_CNT0_VAL - 4 * idx);
}
static void l2x0_pmu_counter_write(int idx, u32 val)
{
writel_relaxed(val, l2x0_base + L2X0_EVENT_CNT0_VAL - 4 * idx);
}
static void __l2x0_pmu_enable(void)
{
u32 val = readl_relaxed(l2x0_base + L2X0_EVENT_CNT_CTRL);
val |= L2X0_EVENT_CNT_CTRL_ENABLE;
writel_relaxed(val, l2x0_base + L2X0_EVENT_CNT_CTRL);
}
static void __l2x0_pmu_disable(void)
{
u32 val = readl_relaxed(l2x0_base + L2X0_EVENT_CNT_CTRL);
val &= ~L2X0_EVENT_CNT_CTRL_ENABLE;
writel_relaxed(val, l2x0_base + L2X0_EVENT_CNT_CTRL);
}
static void l2x0_pmu_enable(struct pmu *pmu)
{
if (l2x0_pmu_num_active_counters() == 0)
return;
__l2x0_pmu_enable();
}
static void l2x0_pmu_disable(struct pmu *pmu)
{
if (l2x0_pmu_num_active_counters() == 0)
return;
__l2x0_pmu_disable();
}
static void warn_if_saturated(u32 count)
{
if (count != 0xffffffff)
return;
pr_warn_ratelimited("L2X0 counter saturated. Poll period too long\n");
}
static void l2x0_pmu_event_read(struct perf_event *event)
{
struct hw_perf_event *hw = &event->hw;
u64 prev_count, new_count, mask;
do {
prev_count = local64_read(&hw->prev_count);
new_count = l2x0_pmu_counter_read(hw->idx);
} while (local64_xchg(&hw->prev_count, new_count) != prev_count);
mask = GENMASK_ULL(31, 0);
local64_add((new_count - prev_count) & mask, &event->count);
warn_if_saturated(new_count);
}
static void l2x0_pmu_event_configure(struct perf_event *event)
{
struct hw_perf_event *hw = &event->hw;
/*
* The L2X0 counters saturate at 0xffffffff rather than wrapping, so we
* will *always* lose some number of events when a counter saturates,
* and have no way of detecting how many were lost.
*
* To minimize the impact of this, we try to maximize the period by
* always starting counters at zero. To ensure that group ratios are
* representative, we poll periodically to avoid counters saturating.
* See l2x0_pmu_poll().
*/
local64_set(&hw->prev_count, 0);
l2x0_pmu_counter_write(hw->idx, 0);
}
static enum hrtimer_restart l2x0_pmu_poll(struct hrtimer *hrtimer)
{
unsigned long flags;
int i;
local_irq_save(flags);
__l2x0_pmu_disable();
for (i = 0; i < PMU_NR_COUNTERS; i++) {
struct perf_event *event = events[i];
if (!event)
continue;
l2x0_pmu_event_read(event);
l2x0_pmu_event_configure(event);
}
__l2x0_pmu_enable();
local_irq_restore(flags);
hrtimer_forward_now(hrtimer, l2x0_pmu_poll_period);
return HRTIMER_RESTART;
}
static void __l2x0_pmu_event_enable(int idx, u32 event)
{
u32 val;
val = event << L2X0_EVENT_CNT_CFG_SRC_SHIFT;
val |= L2X0_EVENT_CNT_CFG_INT_DISABLED;
l2x0_pmu_counter_config_write(idx, val);
}
static void l2x0_pmu_event_start(struct perf_event *event, int flags)
{
struct hw_perf_event *hw = &event->hw;
if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
return;
if (flags & PERF_EF_RELOAD) {
WARN_ON_ONCE(!(hw->state & PERF_HES_UPTODATE));
l2x0_pmu_event_configure(event);
}
hw->state = 0;
__l2x0_pmu_event_enable(hw->idx, hw->config_base);
}
static void __l2x0_pmu_event_disable(int idx)
{
u32 val;
val = L2X0_EVENT_CNT_CFG_SRC_DISABLED << L2X0_EVENT_CNT_CFG_SRC_SHIFT;
val |= L2X0_EVENT_CNT_CFG_INT_DISABLED;
l2x0_pmu_counter_config_write(idx, val);
}
static void l2x0_pmu_event_stop(struct perf_event *event, int flags)
{
struct hw_perf_event *hw = &event->hw;
if (WARN_ON_ONCE(event->hw.state & PERF_HES_STOPPED))
return;
__l2x0_pmu_event_disable(hw->idx);
hw->state |= PERF_HES_STOPPED;
if (flags & PERF_EF_UPDATE) {
l2x0_pmu_event_read(event);
hw->state |= PERF_HES_UPTODATE;
}
}
static int l2x0_pmu_event_add(struct perf_event *event, int flags)
{
struct hw_perf_event *hw = &event->hw;
int idx = l2x0_pmu_find_idx();
if (idx == -1)
return -EAGAIN;
/*
* Pin the timer, so that the overflows are handled by the chosen
* event->cpu (this is the same one as presented in "cpumask"
* attribute).
*/
if (l2x0_pmu_num_active_counters() == 0)
hrtimer_start(&l2x0_pmu_hrtimer, l2x0_pmu_poll_period,
HRTIMER_MODE_REL_PINNED);
events[idx] = event;
hw->idx = idx;
l2x0_pmu_event_configure(event);
hw->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
if (flags & PERF_EF_START)
l2x0_pmu_event_start(event, 0);
return 0;
}
static void l2x0_pmu_event_del(struct perf_event *event, int flags)
{
struct hw_perf_event *hw = &event->hw;
l2x0_pmu_event_stop(event, PERF_EF_UPDATE);
events[hw->idx] = NULL;
hw->idx = -1;
if (l2x0_pmu_num_active_counters() == 0)
hrtimer_cancel(&l2x0_pmu_hrtimer);
}
static bool l2x0_pmu_group_is_valid(struct perf_event
|