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/*
* arch/arm/mach-tegra/dma.c
*
* System DMA driver for NVIDIA Tegra SoCs
*
* Copyright (c) 2008-2009, NVIDIA Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
*/
#include <linux/io.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/spinlock.h>
#include <linux/err.h>
#include <linux/irq.h>
#include <linux/delay.h>
#include <mach/dma.h>
#include <mach/irqs.h>
#include <mach/iomap.h>
#define APB_DMA_GEN 0x000
#define GEN_ENABLE (1<<31)
#define APB_DMA_CNTRL 0x010
#define APB_DMA_IRQ_MASK 0x01c
#define APB_DMA_IRQ_MASK_SET 0x020
#define APB_DMA_CHAN_CSR 0x000
#define CSR_ENB (1<<31)
#define CSR_IE_EOC (1<<30)
#define CSR_HOLD (1<<29)
#define CSR_DIR (1<<28)
#define CSR_ONCE (1<<27)
#define CSR_FLOW (1<<21)
#define CSR_REQ_SEL_SHIFT 16
#define CSR_REQ_SEL_MASK (0x1F<<CSR_REQ_SEL_SHIFT)
#define CSR_REQ_SEL_INVALID (31<<CSR_REQ_SEL_SHIFT)
#define CSR_WCOUNT_SHIFT 2
#define CSR_WCOUNT_MASK 0xFFFC
#define APB_DMA_CHAN_STA 0x004
#define STA_BUSY (1<<31)
#define STA_ISE_EOC (1<<30)
#define STA_HALT (1<<29)
#define STA_PING_PONG (1<<28)
#define STA_COUNT_SHIFT 2
#define STA_COUNT_MASK 0xFFFC
#define APB_DMA_CHAN_AHB_PTR 0x010
#define APB_DMA_CHAN_AHB_SEQ 0x014
#define AHB_SEQ_INTR_ENB (1<<31)
#define AHB_SEQ_BUS_WIDTH_SHIFT 28
#define AHB_SEQ_BUS_WIDTH_MASK (0x7<<AHB_SEQ_BUS_WIDTH_SHIFT)
#define AHB_SEQ_BUS_WIDTH_8 (0<<AHB_SEQ_BUS_WIDTH_SHIFT)
#define AHB_SEQ_BUS_WIDTH_16 (1<<AHB_SEQ_BUS_WIDTH_SHIFT)
#define AHB_SEQ_BUS_WIDTH_32 (2<<AHB_SEQ_BUS_WIDTH_SHIFT)
#define AHB_SEQ_BUS_WIDTH_64 (3<<AHB_SEQ_BUS_WIDTH_SHIFT)
#define AHB_SEQ_BUS_WIDTH_128 (4<<AHB_SEQ_BUS_WIDTH_SHIFT)
#define AHB_SEQ_DATA_SWAP (1<<27)
#define AHB_SEQ_BURST_MASK (0x7<<24)
#define AHB_SEQ_BURST_1 (4<<24)
#define AHB_SEQ_BURST_4 (5<<24)
#define AHB_SEQ_BURST_8 (6<<24)
#define AHB_SEQ_DBL_BUF (1<<19)
#define AHB_SEQ_WRAP_SHIFT 16
#define AHB_SEQ_WRAP_MASK (0x7<<AHB_SEQ_WRAP_SHIFT)
#define APB_DMA_CHAN_APB_PTR 0x018
#define APB_DMA_CHAN_APB_SEQ 0x01c
#define APB_SEQ_BUS_WIDTH_SHIFT 28
#define APB_SEQ_BUS_WIDTH_MASK (0x7<<APB_SEQ_BUS_WIDTH_SHIFT)
#define APB_SEQ_BUS_WIDTH_8 (0<<APB_SEQ_BUS_WIDTH_SHIFT)
#define APB_SEQ_BUS_WIDTH_16 (1<<APB_SEQ_BUS_WIDTH_SHIFT)
#define APB_SEQ_BUS_WIDTH_32 (2<<APB_SEQ_BUS_WIDTH_SHIFT)
#define APB_SEQ_BUS_WIDTH_64 (3<<APB_SEQ_BUS_WIDTH_SHIFT)
#define APB_SEQ_BUS_WIDTH_128 (4<<APB_SEQ_BUS_WIDTH_SHIFT)
#define APB_SEQ_DATA_SWAP (1<<27)
#define APB_SEQ_WRAP_SHIFT 16
#define APB_SEQ_WRAP_MASK (0x7<<APB_SEQ_WRAP_SHIFT)
#define TEGRA_SYSTEM_DMA_CH_NR 16
#define TEGRA_SYSTEM_DMA_AVP_CH_NUM 4
#define TEGRA_SYSTEM_DMA_CH_MIN 0
#define TEGRA_SYSTEM_DMA_CH_MAX \
(TEGRA_SYSTEM_DMA_CH_NR - TEGRA_SYSTEM_DMA_AVP_CH_NUM - 1)
#define NV_DMA_MAX_TRASFER_SIZE 0x10000
const unsigned int ahb_addr_wrap_table[8] = {
0, 32, 64, 128, 256, 512, 1024, 2048
};
const unsigned int apb_addr_wrap_table[8] = {0, 1, 2, 4, 8, 16, 32, 64};
const unsigned int bus_width_table[5] = {8, 16, 32, 64, 128};
#define TEGRA_DMA_NAME_SIZE 16
struct tegra_dma_channel {
struct list_head list;
int id;
spinlock_t lock;
char name[TEGRA_DMA_NAME_SIZE];
void __iomem *addr;
int mode;
int irq;
/* Register shadow */
u32 csr;
u32 ahb_seq;
u32 ahb_ptr;
u32 apb_seq;
u32 apb_ptr;
};
#define NV_DMA_MAX_CHANNELS 32
static DECLARE_BITMAP(channel_usage, NV_DMA_MAX_CHANNELS);
static struct tegra_dma_channel dma_channels[NV_DMA_MAX_CHANNELS];
static void tegra_dma_update_hw(struct tegra_dma_channel *ch,
struct tegra_dma_req *req);
static void tegra_dma_update_hw_partial(struct tegra_dma_channel *ch,
struct tegra_dma_req *req);
static void tegra_dma_init_hw(struct tegra_dma_channel *ch);
static void tegra_dma_stop(struct tegra_dma_channel *ch);
void tegra_dma_flush(struct tegra_dma_channel *ch)
{
}
EXPORT_SYMBOL(tegra_dma_flush);
void tegra_dma_dequeue(struct tegra_dma_channel *ch)
{
struct tegra_dma_req *req;
req = list_entry(ch->list.next, typeof(*req), node);
tegra_dma_dequeue_req(ch, req);
return;
}
void tegra_dma_stop(struct tegra_dma_channel *ch)
{
unsigned int csr;
unsigned int status;
csr = ch->csr;
csr &= ~CSR_IE_EOC;
writel(csr, ch->addr + APB_DMA_CHAN_CSR);
csr &= ~CSR_ENB;
writel(csr, ch->addr + APB_DMA_CHAN_CSR);
status = readl(ch->addr + APB_DMA_CHAN_STA);
if (status & STA_ISE_EOC)
writel(status, ch->addr + APB_DMA_CHAN_STA);
}
int tegra_dma_cancel(struct tegra_dma_channel *ch)
{
unsigned int csr;
unsigned long irq_flags;
spin_lock_irqsave(&ch->lock, irq_flags);
while (!list_empty(&ch->list))
list_del(ch->list.next);
csr = ch->csr;
csr &= ~CSR_REQ_SEL_MASK;
csr |= CSR_REQ_SEL_INVALID;
/* Set the enable as that is not shadowed */
csr |= CSR_ENB;
writel(csr, ch->addr + APB_DMA_CHAN_CSR);
tegra_dma_stop(ch);
spin_unlock_irqrestore(&ch->lock, irq_flags);
return 0;
}
int tegra_dma_dequeue_req(struct tegra_dma_channel *ch,
struct tegra_dma_req *_req)
{
unsigned int csr;
unsigned int status;
struct tegra_dma_req *req = NULL;
int found = 0;
unsigned long irq_flags;
int to_transfer;
int req_transfer_count;
spin_lock_irqsave(&ch->lock, irq_flags);
list_for_each_entry(req, &ch->list, node) {
if (req == _req) {
list_del(&req->node);
found = 1;
break;
}
}
if (!found) {
spin_unlock_irqrestore(&ch->lock, irq_flags);
return 0;
}
/* STOP the DMA and get the transfer count.
* Getting the transfer count is tricky.
* - Change the source selector to invalid to stop the DMA from
* FIFO to memory.
* - Read the status register to know the number of pending
* bytes to be transfered.
* - Finally stop or program the DMA to the next buffer in the
* list.
*/
csr = ch->csr;
csr &= ~CSR_REQ_SEL_MASK;
csr |= CSR_REQ_SEL_INVALID;
/* Set the enable as that is not shadowed */
csr |= CSR_ENB;
writel(csr, ch->addr + APB_DMA_CHAN_CSR);
/* Get the transfer count */
status = readl(ch->addr + APB_DMA_CHAN_STA);
to_transfer = (status & STA_COUNT_MASK) >> STA_COUNT_SHIFT;
req_transfer_count = (ch->csr & CSR_WCOUNT_MASK) >> CSR_WCOUNT_SHIFT;
req_transfer_count += 1;
to_transfer += 1;
req->bytes_transferred = req_transfer_count;
if (status & STA_BUSY)
req->bytes_transferred -= to_transfer;
/* In continous transfer mode, DMA only tracks the count of the
* half DMA buffer. So, if the DMA already finished half the DMA
* then add the half buffer to the completed count.
*
* FIXME: There can be a race here. What if the req to
* dequue happens at the same time as the DMA just moved to
* the new buffer and SW didn't yet received the interrupt?
|