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/*
* R8A7740 processor support
*
* Copyright (C) 2011 Renesas Solutions Corp.
* Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/io.h>
#include <linux/sh_clk.h>
#include <linux/clkdev.h>
#include "clock.h"
#include "common.h"
#include "r8a7740.h"
/*
* | MDx | XTAL1/EXTAL1 | System | EXTALR |
* Clock |-------+-----------------+ clock | 32.768 | RCLK
* Mode | 2/1/0 | src MHz | source | KHz | source
* -------+-------+-----------------+-----------+--------+----------
* 0 | 0 0 0 | External 20~50 | XTAL1 | O | EXTALR
* 1 | 0 0 1 | Crystal 20~30 | XTAL1 | O | EXTALR
* 2 | 0 1 0 | External 40~50 | XTAL1 / 2 | O | EXTALR
* 3 | 0 1 1 | Crystal 40~50 | XTAL1 / 2 | O | EXTALR
* 4 | 1 0 0 | External 20~50 | XTAL1 | x | XTAL1 / 1024
* 5 | 1 0 1 | Crystal 20~30 | XTAL1 | x | XTAL1 / 1024
* 6 | 1 1 0 | External 40~50 | XTAL1 / 2 | x | XTAL1 / 2048
* 7 | 1 1 1 | Crystal 40~50 | XTAL1 / 2 | x | XTAL1 / 2048
*/
/* CPG registers */
#define FRQCRA IOMEM(0xe6150000)
#define FRQCRB IOMEM(0xe6150004)
#define VCLKCR1 IOMEM(0xE6150008)
#define VCLKCR2 IOMEM(0xE615000c)
#define FRQCRC IOMEM(0xe61500e0)
#define FSIACKCR IOMEM(0xe6150018)
#define PLLC01CR IOMEM(0xe6150028)
#define SUBCKCR IOMEM(0xe6150080)
#define USBCKCR IOMEM(0xe615008c)
#define MSTPSR0 IOMEM(0xe6150030)
#define MSTPSR1 IOMEM(0xe6150038)
#define MSTPSR2 IOMEM(0xe6150040)
#define MSTPSR3 IOMEM(0xe6150048)
#define MSTPSR4 IOMEM(0xe615004c)
#define FSIBCKCR IOMEM(0xe6150090)
#define HDMICKCR IOMEM(0xe6150094)
#define SMSTPCR0 IOMEM(0xe6150130)
#define SMSTPCR1 IOMEM(0xe6150134)
#define SMSTPCR2 IOMEM(0xe6150138)
#define SMSTPCR3 IOMEM(0xe615013c)
#define SMSTPCR4 IOMEM(0xe6150140)
#define FSIDIVA IOMEM(0xFE1F8000)
#define FSIDIVB IOMEM(0xFE1F8008)
/* Fixed 32 KHz root clock from EXTALR pin */
static struct clk extalr_clk = {
.rate = 32768,
};
/*
* 25MHz default rate for the EXTAL1 root input clock.
* If needed, reset this with clk_set_rate() from the platform code.
*/
static struct clk extal1_clk = {
.rate = 25000000,
};
/*
* 48MHz default rate for the EXTAL2 root input clock.
* If needed, reset this with clk_set_rate() from the platform code.
*/
static struct clk extal2_clk = {
.rate = 48000000,
};
/*
* 27MHz default rate for the DV_CLKI root input clock.
* If needed, reset this with clk_set_rate() from the platform code.
*/
static struct clk dv_clk = {
.rate = 27000000,
};
SH_CLK_RATIO(div2, 1, 2);
SH_CLK_RATIO(div1k, 1, 1024);
SH_FIXED_RATIO_CLK(extal1_div2_clk, extal1_clk, div2);
SH_FIXED_RATIO_CLK(extal1_div1024_clk, extal1_clk, div1k);
SH_FIXED_RATIO_CLK(extal1_div2048_clk, extal1_div2_clk, div1k);
SH_FIXED_RATIO_CLK(extal2_div2_clk, extal2_clk, div2);
static struct sh_clk_ops followparent_clk_ops = {
.recalc = followparent_recalc,
};
/* Main clock */
static struct clk system_clk = {
.ops = &followparent_clk_ops,
};
SH_FIXED_RATIO_CLK(system_div2_clk, system_clk, div2);
/* r_clk */
static struct clk r_clk = {
.ops = &followparent_clk_ops,
};
/* PLLC0/PLLC1 */
static unsigned long pllc01_recalc(struct clk *clk)
{
unsigned long mult = 1;
if (__raw_readl(PLLC01CR) & (1 << 14))
mult = ((__raw_readl(clk->enable_reg) >> 24) & 0x7f) + 1;
return clk->parent->rate * mult;
}
static struct sh_clk_ops pllc01_clk_ops = {
.recalc = pllc01_recalc,
};
static struct clk pllc0_clk = {
.ops = &pllc01_clk_ops,
.flags = CLK_ENABLE_ON_INIT,
.parent = &system_clk,
.enable_reg = (void __iomem *)FRQCRC,
};
static struct clk pllc1_clk = {
.ops = &pllc01_clk_ops,
.flags = CLK_ENABLE_ON_INIT,
.parent = &system_div2_clk,
.enable_reg = (void __iomem *)FRQCRA,
};
/* PLLC1 / 2 */
SH_FIXED_RATIO_CLK(pllc1_div2_clk, pllc1_clk, div2);
/* USB clock */
/*
* USBCKCR is controlling usb24 clock
* bit[7] : parent clock
* bit[6] : clock divide rate
* And this bit[7] is used as a "usb24s" from other devices.
* (Video clock / Sub clock / SPU clock)
* You can controll this clock as a below.
*
* struct clk *usb24 = clk_get(dev, "usb24");
* struct clk *usb24s = clk_get(NULL, "usb24s");
* struct clk *system = clk_get(NULL, "system_clk");
* int rate = clk_get_rate(system);
*
* clk_set_parent(usb24s, system); // for bit[7]
* clk_set_rate(usb24, rate / 2); // for bit[6]
*/
static struct clk *usb24s_parents[] = {
[0] = &system_clk,
[1] = &extal2_clk
};
static int usb24s_enable(struct clk *clk)
{
__raw_writel(__raw_readl(USBCKCR) & ~(1 << 8), USBCKCR);
return 0;
}
static void usb24s_disable(struct clk *clk)
{
__raw_writel(__raw_readl(USBCKCR) | (1 << 8), USBCKCR);
}
static int usb24s_set_parent(struct clk *clk, struct clk *parent)
{
int i, ret;
u32 val;
if (!clk->parent_table || !clk->parent_num)
return -EINVAL;
/* Search the parent */
for (i = 0; i < clk->parent_num; i++)
if (clk->parent_table[i] == parent)
break;
if (i == clk->parent_num)
return -ENODEV;
ret = clk_reparent(clk, parent);
if (ret < 0)
return ret;
val = __raw_readl(USBCKCR);
val &= ~(1 << 7);
val |= i << 7;
__raw_writel(val, USBCKCR);
return 0;
}
static struct sh_clk_ops usb24s_clk_ops = {
.recalc = followparent_recalc,
.enable = usb24s_enable,
.disable = usb24s_disable,
.set_parent = usb24s_set_parent,
};
static struct clk usb24s_clk = {
.ops = &usb24s_clk_ops,
.parent_table = usb24s_parents,
.parent_num = ARRAY_SIZE(usb24s_parents),
.parent = &system_clk,
};
static unsigned long usb24_recalc(struct clk *clk)
{
return clk->parent->rate /
((__raw_readl(USBCKCR) & (1 << 6)) ? 1 : 2);
};
static int usb24_set_rate(struct clk *clk, unsigned long rate)
{
u32 val;
/* closer to which ? parent->rate or parent->rate/2 */
val = __raw_readl(USBCKCR);
val &= ~(1 << 6);
val |= (rate > (clk->parent->rate / 4) * 3) << 6;
__raw_writel(val, USBCKCR);
return 0;
}
static struct sh_clk_ops usb24_clk_ops = {
.recalc = usb24_recalc,
.set_rate = usb24_set_rate,
};
static struct clk usb24_clk = {
.ops = &usb24_clk_ops,
.parent = &usb24s_clk,
};
/* External FSIACK/FSIBCK clock */
static struct clk fsiack_clk = {
};
static
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