1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
|
/*
* Clock tree for CSR SiRFprimaII
*
* Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
*
* Licensed under GPLv2 or later.
*/
#include <linux/module.h>
#include <linux/bitops.h>
#include <linux/err.h>
#include <linux/errno.h>
#include <linux/io.h>
#include <linux/clkdev.h>
#include <linux/clk.h>
#include <linux/spinlock.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <asm/mach/map.h>
#include <mach/map.h>
#define SIRFSOC_CLKC_CLK_EN0 0x0000
#define SIRFSOC_CLKC_CLK_EN1 0x0004
#define SIRFSOC_CLKC_REF_CFG 0x0014
#define SIRFSOC_CLKC_CPU_CFG 0x0018
#define SIRFSOC_CLKC_MEM_CFG 0x001c
#define SIRFSOC_CLKC_SYS_CFG 0x0020
#define SIRFSOC_CLKC_IO_CFG 0x0024
#define SIRFSOC_CLKC_DSP_CFG 0x0028
#define SIRFSOC_CLKC_GFX_CFG 0x002c
#define SIRFSOC_CLKC_MM_CFG 0x0030
#define SIRFSOC_LKC_LCD_CFG 0x0034
#define SIRFSOC_CLKC_MMC_CFG 0x0038
#define SIRFSOC_CLKC_PLL1_CFG0 0x0040
#define SIRFSOC_CLKC_PLL2_CFG0 0x0044
#define SIRFSOC_CLKC_PLL3_CFG0 0x0048
#define SIRFSOC_CLKC_PLL1_CFG1 0x004c
#define SIRFSOC_CLKC_PLL2_CFG1 0x0050
#define SIRFSOC_CLKC_PLL3_CFG1 0x0054
#define SIRFSOC_CLKC_PLL1_CFG2 0x0058
#define SIRFSOC_CLKC_PLL2_CFG2 0x005c
#define SIRFSOC_CLKC_PLL3_CFG2 0x0060
#define SIRFSOC_CLOCK_VA_BASE SIRFSOC_VA(0x005000)
#define KHZ 1000
#define MHZ (KHZ * KHZ)
struct clk_ops {
unsigned long (*get_rate)(struct clk *clk);
long (*round_rate)(struct clk *clk, unsigned long rate);
int (*set_rate)(struct clk *clk, unsigned long rate);
int (*enable)(struct clk *clk);
int (*disable)(struct clk *clk);
struct clk *(*get_parent)(struct clk *clk);
int (*set_parent)(struct clk *clk, struct clk *parent);
};
struct clk {
struct clk *parent; /* parent clk */
unsigned long rate; /* clock rate in Hz */
signed char usage; /* clock enable count */
signed char enable_bit; /* enable bit: 0 ~ 63 */
unsigned short regofs; /* register offset */
struct clk_ops *ops; /* clock operation */
};
static DEFINE_SPINLOCK(clocks_lock);
static inline unsigned long clkc_readl(unsigned reg)
{
return readl(SIRFSOC_CLOCK_VA_BASE + reg);
}
static inline void clkc_writel(u32 val, unsigned reg)
{
writel(val, SIRFSOC_CLOCK_VA_BASE + reg);
}
/*
* osc_rtc - real time oscillator - 32.768KHz
* osc_sys - high speed oscillator - 26MHz
*/
static struct clk clk_rtc = {
.rate = 32768,
};
static struct clk clk_osc = {
.rate = 26 * MHZ,
};
/*
* std pll
*/
static unsigned long std_pll_get_rate(struct clk *clk)
{
unsigned long fin = clk_get_rate(clk->parent);
u32 regcfg2 = clk->regofs + SIRFSOC_CLKC_PLL1_CFG2 -
SIRFSOC_CLKC_PLL1_CFG0;
if (clkc_readl(regcfg2) & BIT(2)) {
/* pll bypass mode */
clk->rate = fin;
} else {
/* fout = fin * nf / nr / od */
u32 cfg0 = clkc_readl(clk->regofs);
u32 nf = (cfg0 & (BIT(13) - 1)) + 1;
u32 nr = ((cfg0 >> 13) & (BIT(6) - 1)) + 1;
u32 od = ((cfg0 >> 19) & (BIT(4) - 1)) + 1;
WARN_ON(fin % MHZ);
clk->rate = fin / MHZ * nf / nr / od * MHZ;
}
return clk->rate;
}
static int std_pll_set_rate(struct clk *clk, unsigned long rate)
{
unsigned long fin, nf, nr, od, reg;
/*
* fout = fin * nf / (nr * od);
* set od = 1, nr = fin/MHz, so fout = nf * MHz
*/
nf = rate / MHZ;
if (unlikely((rate % MHZ) || nf > BIT(13) || nf < 1))
return -EINVAL;
fin = clk_get_rate(clk->parent);
BUG_ON(fin < MHZ);
nr = fin / MHZ;
BUG_ON((fin % MHZ) || nr > BIT(6));
od = 1;
reg = (nf - 1) | ((nr - 1) << 13) | ((od - 1) << 19);
clkc_writel(reg, clk->regofs);
reg = clk->regofs + SIRFSOC_CLKC_PLL1_CFG1 - SIRFSOC_CLKC_PLL1_CFG0;
clkc_writel((nf >> 1) - 1, reg);
reg = clk->regofs + SIRFSOC_CLKC_PLL1_CFG2 - SIRFSOC_CLKC_PLL1_CFG0;
while (!(clkc_readl(reg) & BIT(6)))
cpu_relax();
clk->rate = 0; /* set to zero will force recalculation */
return 0;
}
static struct clk_ops std_pll_ops = {
.get_rate = std_pll_get_rate,
.set_rate = std_pll_set_rate,
};
static struct clk clk_pll1 = {
.parent = &clk_osc,
.regofs = SIRFSOC_CLKC_PLL1_CFG0,
.ops = &std_pll_ops,
};
static struct clk clk_pll2 = {
.parent = &clk_osc,
.regofs = SIRFSOC_CLKC_PLL2_CFG0,
.ops = &std_pll_ops,
};
static struct clk clk_pll3 = {
.parent = &clk_osc,
.regofs = SIRFSOC_CLKC_PLL3_CFG0,
.ops = &std_pll_ops,
};
/*
* clock domains - cpu, mem, sys/io
*/
static struct clk clk_mem;
static struct clk *dmn_get_parent(struct clk *clk)
{
struct clk *clks[] = {
&clk_osc, &clk_rtc, &clk_pll1, &clk_pll2, &clk_pll3
};
u32 cfg = clkc_readl(clk->regofs);
WARN_ON((cfg & (BIT(3) - 1)) > 4);
return clks[cfg & (BIT(3) - 1)];
}
static int dmn_set_parent(struct clk *clk, struct clk *parent)
{
const struct clk *clks[] = {
&clk_osc, &clk_rtc, &clk_pll1, &clk_pll2, &clk_pll3
};
u32 cfg = clkc_readl(clk->regofs);
int i;
for (i = 0; i < ARRAY_SIZE(clks); i++) {
if (clks[i] == parent) {
cfg &= ~(BIT(3) - 1);
clkc_writel(cfg | i, clk->regofs);
/* BIT(3) - switching status: 1 - busy, 0 - done */
while (clkc_readl(clk->regofs) & BIT(3))
cpu_relax();
return 0;
}
}
return -EINVAL;
}
static unsigned long dmn_get_rate(struct clk *clk)
{
unsigned long fin = clk_get_rate(clk->parent);
u32 cfg = clkc_readl(clk->regofs);
if (cfg & BIT(24)) {
/* fcd bypass mode */
clk->rate = fin;
} else {
/*
* wait count: bit[19:16], hold count: bit[23:20]
*/
u32 wait = (cfg >> 16) & (BIT(4) - 1);
u32 hold = (cfg >>
|