/*
* Copyright (C) 2013 Texas Instruments Incorporated
*
* Hwmod present only in AM43x and those that differ other than register
* offsets as compared to AM335x.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include "omap_hwmod.h"
#include "omap_hwmod_33xx_43xx_common_data.h"
#include "prcm43xx.h"
#include "omap_hwmod_common_data.h"
#include "hdq1w.h"
/* IP blocks */
static struct omap_hwmod am43xx_emif_hwmod = {
.name = "emif",
.class = &am33xx_emif_hwmod_class,
.clkdm_name = "emif_clkdm",
.flags = HWMOD_INIT_NO_IDLE,
.main_clk = "dpll_ddr_m2_ck",
.prcm = {
.omap4 = {
.clkctrl_offs = AM43XX_CM_PER_EMIF_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
static struct omap_hwmod am43xx_l4_hs_hwmod = {
.name = "l4_hs",
.class = &am33xx_l4_hwmod_class,
.clkdm_name = "l3_clkdm",
.flags = HWMOD_INIT_NO_IDLE,
.main_clk = "l4hs_gclk",
.prcm = {
.omap4 = {
.clkctrl_offs = AM43XX_CM_PER_L4HS_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = {
{ .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 },
};
static struct omap_hwmod am43xx_wkup_m3_hwmod = {
.name = "wkup_m3",
.class = &am33xx_wkup_m3_hwmod_class,
.clkdm_name = "l4_wkup_aon_clkdm",
/* Keep hardreset asserted */
.flags = HWMOD_INIT_NO_RESET | HWMOD_NO_IDLEST,
.main_clk = "sys_clkin_ck",
.prcm = {
.omap4 = {
.clkctrl_offs = AM43XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
.rstctrl_offs = AM43XX_RM_WKUP_RSTCTRL_OFFSET,
.rstst_offs = AM43XX_RM_WKUP_RSTST_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
.rst_lines = am33xx_wkup_m3_resets,
.rst_lines_cnt = ARRAY_SIZE(am33xx_wkup_m3_resets),
};
static struct omap_hwmod am43xx_control_hwmod = {
.name = "control",
.class = &am33xx_control_hwmod_class,
.clkdm_name = "l4_wkup_clkdm",
.flags = HWMOD_INIT_NO_IDLE,
.main_clk = "sys_clkin_ck",
.prcm = {
.omap4 = {
.clkctrl_offs = AM43XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
static struct omap_hwmod_class_sysconfig am43xx_synctimer_sysc = {
.rev_offs = 0x0,
.sysc_offs = 0x4,
.sysc_flags = SYSC_HAS_SIDLEMODE,
.idlemodes = (SIDLE_FORCE | SIDLE_NO),
.sysc_fields = &omap_hwmod_sysc_type1,
};
static struct omap_hwmod_class am43xx_synctimer_hwmod_class = {
.name = "synctimer",
.sysc = &am43xx_synctimer_sysc,
};
static struct omap_hwmod am43xx_synctimer_hwmod = {
.name = "counter_32k",
.class = &am43xx_synctimer_hwmod_class,
.clkdm_name = "l4_wkup_aon_clkdm",
.flags = HWMOD_SWSUP_SIDLE,
.main_clk = "synctimer_32kclk",
.prcm = {
.omap4 = {
.clkctrl_offs = AM43XX_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
static struct omap_hwmod am43xx_timer8_hwmod = {
.name = "timer8",
.class = &am33xx_timer_hwmod_class,
.clkdm_name = "l4ls_clkdm",
.main_clk = "timer8_fck",
.prcm = {
.omap4 = {
.clkctrl_offs = AM43XX_CM_PER_TIMER8_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
static struct omap_hwmod am43xx_timer9_hwmod = {
.name = "timer9",
.class = &am33xx_timer_hwmod_class,
.clkdm_name = "l4ls_clkdm",
.main_clk = "timer9_fck",
.prcm = {
.omap4 = {
.clkctrl_offs = AM43XX_CM_PER_TIMER9_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
static struct omap_hwmod am43xx_timer10_hwmod = {
.name = "timer10",
.class = &am33xx_timer_hwmod_class,
.clkdm_name = "l4ls_clkdm",
.main_clk = "timer10_fck",
.prcm = {
.omap4 = {
.clkctrl_offs = AM43XX_CM_PER_TIMER10_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,
},
},
};
static struct omap_hwmod am43xx_timer11_hwmod = {
.name = "timer11",
.class = &am33xx_timer_hwmod_class,
.clkdm_name = "l4ls_clkdm",
.main_clk = "timer11_fck",
.prcm = {
.omap4 = {
.clkctrl_offs = AM43XX_CM_PER_TIMER11_CLKCTRL_OFFSET,
.modulemode = MODULEMODE_SWCTRL,