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/*
* Goramo MultiLink router platform code
* Copyright (C) 2006-2009 Krzysztof Halasa <khc@pm.waw.pl>
*/
#include <linux/delay.h>
#include <linux/gpio.h>
#include <linux/hdlc.h>
#include <linux/i2c-gpio.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/serial_8250.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/flash.h>
#include <asm/mach/pci.h>
#include <asm/system_info.h>
#define SLOT_ETHA 0x0B /* IDSEL = AD21 */
#define SLOT_ETHB 0x0C /* IDSEL = AD20 */
#define SLOT_MPCI 0x0D /* IDSEL = AD19 */
#define SLOT_NEC 0x0E /* IDSEL = AD18 */
/* GPIO lines */
#define GPIO_SCL 0
#define GPIO_SDA 1
#define GPIO_STR 2
#define GPIO_IRQ_NEC 3
#define GPIO_IRQ_ETHA 4
#define GPIO_IRQ_ETHB 5
#define GPIO_HSS0_DCD_N 6
#define GPIO_HSS1_DCD_N 7
#define GPIO_UART0_DCD 8
#define GPIO_UART1_DCD 9
#define GPIO_HSS0_CTS_N 10
#define GPIO_HSS1_CTS_N 11
#define GPIO_IRQ_MPCI 12
#define GPIO_HSS1_RTS_N 13
#define GPIO_HSS0_RTS_N 14
/* GPIO15 is not connected */
/* Control outputs from 74HC4094 */
#define CONTROL_HSS0_CLK_INT 0
#define CONTROL_HSS1_CLK_INT 1
#define CONTROL_HSS0_DTR_N 2
#define CONTROL_HSS1_DTR_N 3
#define CONTROL_EXT 4
#define CONTROL_AUTO_RESET 5
#define CONTROL_PCI_RESET_N 6
#define CONTROL_EEPROM_WC_N 7
/* offsets from start of flash ROM = 0x50000000 */
#define CFG_ETH0_ADDRESS 0x40 /* 6 bytes */
#define CFG_ETH1_ADDRESS 0x46 /* 6 bytes */
#define CFG_REV 0x4C /* u32 */
#define CFG_SDRAM_SIZE 0x50 /* u32 */
#define CFG_SDRAM_CONF 0x54 /* u32 */
#define CFG_SDRAM_MODE 0x58 /* u32 */
#define CFG_SDRAM_REFRESH 0x5C /* u32 */
#define CFG_HW_BITS 0x60 /* u32 */
#define CFG_HW_USB_PORTS 0x00000007 /* 0 = no NEC chip, 1-5 = ports # */
#define CFG_HW_HAS_PCI_SLOT 0x00000008
#define CFG_HW_HAS_ETH0 0x00000010
#define CFG_HW_HAS_ETH1 0x00000020
#define CFG_HW_HAS_HSS0 0x00000040
#define CFG_HW_HAS_HSS1 0x00000080
#define CFG_HW_HAS_UART0 0x00000100
#define CFG_HW_HAS_UART1 0x00000200
#define CFG_HW_HAS_EEPROM 0x00000400
#define FLASH_CMD_READ_ARRAY 0xFF
#define FLASH_CMD_READ_ID 0x90
#define FLASH_SER_OFF 0x102 /* 0x81 in 16-bit mode */
static u32 hw_bits = 0xFFFFFFFD; /* assume all hardware present */;
static u8 control_value;
static void set_scl(u8 value)
{
gpio_set_value(GPIO_SCL, !!value);
udelay(3);
}
static void set_sda(u8 value)
{
gpio_set_value(GPIO_SDA, !!value);
udelay(3);
}
static void set_str(u8 value)
{
gpio_set_value(GPIO_STR, !!value);
udelay(3);
}
static inline void set_control(int line, int value)
{
if (value)
control_value |= (1 << line);
else
control_value &= ~(1 << line);
}
static void output_control(void)
{
int i;
gpio_direction_output(GPIO_SCL, 1);
gpio_direction_output(GPIO_SDA, 1);
for (i = 0; i < 8; i++) {
set_scl(0);
set_sda(control_value & (0x80 >> i)); /* MSB first */
set_scl(1); /* active edge */
}
set_str(1);
set_str(0);
set_scl(0);
set_sda(1); /* Be ready for START */
set_scl(1);
}
static void (*set_carrier_cb_tab[2])(void *pdev, int carrier);
static int hss_set_clock(int port, unsigned int clock_type)
{
int ctrl_int = port ? CONTROL_HSS1_CLK_INT : CONTROL_HSS0_CLK_INT;
switch (clock_type) {
case CLOCK_DEFAULT:
case CLOCK_EXT:
set_control(ctrl_int, 0);
output_control();
return CLOCK_EXT;
case CLOCK_INT:
set_control(ctrl_int, 1);
output_control();
return CLOCK_INT;
default:
return -EINVAL;
}
}
static irqreturn_t hss_dcd_irq(int irq, void *pdev)
{
int port = (irq == IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N));
int i = gpio_get_value(port ? GPIO_HSS1_DCD_N : GPIO_HSS0_DCD_N);
set_carrier_cb_tab[port](pdev, !i);
return IRQ_HANDLED;
}
static int hss_open(int port, void *pdev,
void (*set_carrier_cb)(void *pdev, int carrier))
{
int i, irq;
if (!port)
irq = IXP4XX_GPIO_IRQ(GPIO_HSS0_DCD_N);
else
irq = IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N);
i = gpio_get_value(port ? GPIO_HSS1_DCD_N : GPIO_HSS0_DCD_N);
set_carrier_cb(pdev, !i);
set_carrier_cb_tab[!!port] = set_carrier_cb;
if ((i = request_irq(irq, hss_dcd_irq, 0, "IXP4xx HSS", pdev)) != 0) {
printk(KERN_ERR "ixp4xx_hss: failed to request IRQ%i (%i)\n",
irq, i);
return i;
}
set_control(port ? CONTROL_HSS1_DTR_N : CONTROL_HSS0_DTR_N, 0);
output_control();
gpio_set_value(port ? GPIO_HSS1_RTS_N : GPIO_HSS0_RTS_N, 0);
return 0;
}
static void hss_close(int port, void *pdev)
{
free_irq(port ? IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N) :
IXP4XX_GPIO_IRQ(GPIO_HSS0_DCD_N), pdev);
set_carrier_cb_tab[!!port] = NULL; /* catch bugs */
set_control(port ? CONTROL_HSS1_DTR_N : CONTROL_HSS0_DTR_N, 1);
output_control();
gpio_set_value(port ? GPIO_HSS1_RTS_N : GPIO_HSS0_RTS_N, 1);
}
/* Flash memory */
static struct flash_platform_data flash_data = {
.map_name = "cfi_probe",
.width = 2,
};
static struct resource flash_resource = {
.flags = IORESOURCE_MEM,
};
static struct platform_device device_flash = {
.name = "IXP4XX-Flash",
.id = 0,
.dev = { .platform_data = &flash_data },
.num_resources = 1,
.resource = &flash_resource,
};
/* I^2C interface */
static struct i2c_gpio_platform_data i2c_data = {
.sda_pin = GPIO_SDA,
.scl_pin = GPIO_SCL,
};
static struct platform_device device_i2c = {
.name = "i2c-gpio",
.id = 0,
.dev = { .platform_data = &i2c_data },
};
/* IXP425 2 UART ports */
static struct resource uart_resources[] = {
{
.start = IXP4XX_UART1_BASE_PHYS,
.end = IXP4XX_UART1_BASE_PHYS + 0x0fff,
.flags = IORESOURCE_MEM,
},
{
.start = IXP4XX_UART2_BASE_PHYS,
.end = IXP4XX_UART2_BASE_PHYS + 0x0fff,
.flags = IORESOURCE_MEM,
}
};
static struct plat_serial8250_port uart_data[] = {
{
.mapbase = IXP4XX_UART1_BASE_PHYS,
.membase = (char __iomem *)IXP4XX_UART1_BASE_VIRT +
REG_OFFSET,
.irq = IRQ_IXP4XX_UART1,
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
.iotype = UPIO_MEM,
.regshift = 2,
.uartclk = IXP4XX_UART_XTAL,
},
{
.mapbase = IXP4XX_UART2_BASE_PHYS,
.membase = (char __iomem *)IXP4XX_UART2_BASE_VIRT +
REG_OFFSET,
.irq = IRQ_IXP4XX_UART2,
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
.iotype = UPIO_MEM,
.regshift = 2,
.uartclk = IXP4XX_UART_XTAL,
},
{ },
};
static struct platform_device device_uarts = {
.name = "serial8250",
.id = PLAT8250_DEV_PLATFORM,
.dev.platform_data = uart_data,
.num_resources = 2,
.resource = uart_resources,
};
/* Built-in 10/100 Ethernet MAC interfaces */
static struct eth_plat_info eth_plat[] = {
{
.phy = 0,
.rxq = 3,
.txreadyq = 32,
}, {
.phy = 1,
.rxq = 4,
.txreadyq = 33,
}
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