/*
* TI DA830/OMAP L137 chip specific setup
*
* Author: Mark A. Greer <mgreer@mvista.com>
*
* 2009 (c) MontaVista Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*/
#include <linux/clk-provider.h>
#include <linux/clk/davinci.h>
#include <linux/gpio.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/irqchip/irq-davinci-cp-intc.h>
#include <linux/platform_data/gpio-davinci.h>
#include <asm/mach/map.h>
#include <mach/common.h>
#include <mach/cputype.h>
#include <mach/da8xx.h>
#include <clocksource/timer-davinci.h>
#include "irqs.h"
#include "mux.h"
/* Offsets of the 8 compare registers on the da830 */
#define DA830_CMP12_0 0x60
#define DA830_CMP12_1 0x64
#define DA830_CMP12_2 0x68
#define DA830_CMP12_3 0x6c
#define DA830_CMP12_4 0x70
#define DA830_CMP12_5 0x74
#define DA830_CMP12_6 0x78
#define DA830_CMP12_7 0x7c
#define DA830_REF_FREQ 24000000
/*
* Device specific mux setup
*
* soc description mux mode mode mux dbg
* reg offset mask mode
*/
static const struct mux_config da830_pins[] = {
#ifdef CONFIG_DAVINCI_MUX
MUX_CFG(DA830, GPIO7_14, 0, 0, 0xf, 1, false)
MUX_CFG(DA830, RTCK, 0, 0, 0xf, 8, false)
MUX_CFG(DA830, GPIO7_15, 0, 4, 0xf, 1, false)
MUX_CFG(DA830, EMU_0, 0, 4, 0xf, 8, false)
MUX_CFG(DA830, EMB_SDCKE, 0, 8, 0xf, 1, false)
MUX_CFG(DA830, EMB_CLK_GLUE, 0, 12, 0xf, 1, false)
MUX_CFG(DA830, EMB_CLK, 0, 12, 0xf, 2, false)
MUX_CFG(DA830, NEMB_CS_0, 0, 16, 0xf, 1, false)
MUX_CFG(DA830, NEMB_CAS, 0, 20, 0xf, 1, false)
MUX_CFG(DA830, NEMB_RAS, 0, 24, 0xf, 1, false)
MUX_CFG(DA830, NEMB_WE, 0, 28, 0xf, 1, false)
MUX_CFG(DA830, EMB_BA_1, 1, 0, 0xf, 1, false)
MUX_CFG(DA830, EMB_BA_0, 1, 4, 0xf, 1, false)
MUX_CFG(DA830, EMB_A_0, 1, 8, 0xf, 1, false)
MUX_CFG(DA830, EMB_A_1, 1, 12, 0xf, 1, false)
MUX_CFG(DA830, EMB_A_2, 1, 16, 0xf, 1, false)
MUX_CFG(DA830, EMB_A_3, 1, 20, 0xf, 1, false)
MUX_CFG(DA830, EMB_A_4, 1, 24, 0xf, 1, false)
MUX_CFG(DA830, EMB_A_5, 1, 28, 0xf, 1, false)
MUX_CFG(DA830, GPIO7_0, 1, 0, 0xf, 8, false)
MUX_CFG(DA830, GPIO7_1, 1, 4, 0xf, 8, false)
MUX_CFG(DA830, GPIO7_2, 1, 8, 0xf, 8, false)
MUX_CFG(DA830, GPIO7_3, 1, 12, 0xf, 8, false)
MUX_CFG(DA830, GPIO7_4, 1, 16, 0xf, 8, false)
MUX_CFG(DA830, GPIO7_5, 1, 20, 0xf, 8, false)
MUX_CFG(DA830, GPIO7_6, 1, 24, 0xf, 8, false)
MUX_CFG(DA830, GPIO7_7, 1, 28, 0xf, 8, false)
MUX_CFG(DA830, EMB_A_6, 2, 0, 0xf, 1, false)
MUX_CFG(DA830, EMB_A_7, 2, 4, 0xf, 1, false)
MUX_CFG(DA830, EMB_A_8, 2, 8, 0xf, 1, false)
MUX_CFG(DA830, EMB_A_9, 2, 12, 0xf, 1, false)
MUX_CFG(DA830, EMB_A_10, 2, 16, 0xf, 1, false)
MUX_CFG(DA830, EMB_A_11, 2, 20, 0xf, 1, false)
MUX_CFG(DA830, EMB_A_12, 2, 24, 0xf, 1, false)
MUX_CFG(DA830, EMB_D_31, 2, 28, 0xf, 1, false)
MUX_CFG(DA830, GPIO7_8, 2, 0, 0xf, 8, false)
MUX_CFG(DA830, GPIO7_9, 2, 4, 0xf, 8, false)
MUX_CFG(DA830, GPIO7_10, 2, 8, 0xf, 8, false)
MUX_CFG(DA830, GPIO7_11, 2, 12, 0xf, 8, false)
MUX_CFG(DA830, GPIO7_12, 2, 16, 0xf, 8, false)
MUX_CFG(DA830, GPIO7_13, 2, 20, 0xf, 8, false)
MUX_CFG(DA830, GPIO3_13, 2, 24, 0xf, 8, false)
MUX_CFG(DA830, EMB_D_30, 3, 0, 0xf, 1, false)
MUX_CFG(DA830, EMB_D_29, 3, 4, 0xf, 1, false)
MUX_CFG(DA830, EMB_D_28, 3, 8, 0xf, 1, false)
MUX_CFG(DA830, EMB_D_27, 3, 12, 0xf, 1, false)
MUX_CFG(DA830, EMB_D_26, 3, 16, 0xf, 1, false)
MUX_CFG(DA830, EMB_D_25,