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/*
* PCI-E support for CNS3xxx
*
* Copyright 2008 Cavium Networks
* Richard Liu <richard.liu@caviumnetworks.com>
* Copyright 2010 MontaVista Software, LLC.
* Anton Vorontsov <avorontsov@mvista.com>
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
* published by the Free Software Foundation.
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/bug.h>
#include <linux/pci.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/interrupt.h>
#include <linux/ptrace.h>
#include <asm/mach/map.h>
#include <mach/cns3xxx.h>
#include "core.h"
enum cns3xxx_access_type {
CNS3XXX_HOST_TYPE = 0,
CNS3XXX_CFG0_TYPE,
CNS3XXX_CFG1_TYPE,
CNS3XXX_NUM_ACCESS_TYPES,
};
struct cns3xxx_pcie {
struct map_desc cfg_bases[CNS3XXX_NUM_ACCESS_TYPES];
unsigned int irqs[2];
struct resource res_io;
struct resource res_mem;
struct hw_pci hw_pci;
bool linked;
};
static struct cns3xxx_pcie cns3xxx_pcie[]; /* forward decl. */
static struct cns3xxx_pcie *sysdata_to_cnspci(void *sysdata)
{
struct pci_sys_data *root = sysdata;
return &cns3xxx_pcie[root->domain];
}
static struct cns3xxx_pcie *pdev_to_cnspci(const struct pci_dev *dev)
{
return sysdata_to_cnspci(dev->sysdata);
}
static struct cns3xxx_pcie *pbus_to_cnspci(struct pci_bus *bus)
{
return sysdata_to_cnspci(bus->sysdata);
}
static void __iomem *cns3xxx_pci_cfg_base(struct pci_bus *bus,
unsigned int devfn, int where)
{
struct cns3xxx_pcie *cnspci = pbus_to_cnspci(bus);
int busno = bus->number;
int slot = PCI_SLOT(devfn);
int offset;
enum cns3xxx_access_type type;
void __iomem *base;
/* If there is no link, just show the CNS PCI bridge. */
if (!cnspci->linked && (busno > 0 || slot > 0))
return NULL;
/*
* The CNS PCI bridge doesn't fit into the PCI hierarchy, though
* we still want to access it. For this to work, we must place
* the first device on the same bus as the CNS PCI bridge.
*/
if (busno == 0) {
if (slot > 1)
return NULL;
type = slot;
} else {
type = CNS3XXX_CFG1_TYPE;
}
base = (void __iomem *)cnspci->cfg_bases[type].virtual;
offset = ((busno & 0xf) << 20) | (devfn << 12) | (where & 0xffc);
return base + offset;
}
static int cns3xxx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
int where, int size, u32 *val)
{
u32 v;
void __iomem *base;
u32 mask = (0x1ull << (size * 8)) - 1;
int shift = (where % 4) * 8;
base = cns3xxx_pci_cfg_base(bus, devfn, where);
if (!base) {
*val = 0xffffffff;
return PCIBIOS_SUCCESSFUL;
}
v = __raw_readl(base);
if (bus->number == 0 && devfn == 0 &&
(where & 0xffc) == PCI_CLASS_REVISION) {
/*
* RC's class is 0xb, but Linux PCI driver needs 0x604
* for a PCIe bridge. So we must fixup the class code
* to 0x604 here.
*/
v &= 0xff;
v |= 0x604 << 16;
}
*val = (v >> shift) & mask;
return PCIBIOS_SUCCESSFUL;
}
static int cns3xxx_pci_write_config(struct pci_bus *bus, unsigned int devfn,
int where, int size, u32 val)
{
u32 v;
void __iomem *base;
u32 mask = (0x1ull << (size * 8)) - 1;
int shift = (where % 4) * 8;
base = cns3xxx_pci_cfg_base(bus, devfn, where);
if (!base)
return PCIBIOS_SUCCESSFUL;
v = __raw_readl(base);
v &= ~(mask << shift);
v |= (val & mask) << shift;
__raw_writel(v, base);
return PCIBIOS_SUCCESSFUL;
}
static int cns3xxx_pci_setup(int nr, struct pci_sys_data *sys)
{
struct cns3xxx_pcie *cnspci = sysdata_to_cnspci(sys);
struct resource *res_io = &cnspci->res_io;
struct resource *res_mem = &cnspci->res_mem;
BUG_ON(request_resource(&iomem_resource, res_io) ||
request_resource(&iomem_resource, res_mem));
pci_add_resource_offset(&sys->resources, res_io, sys->io_offset);
pci_add_resource_offset(&sys->resources, res_mem, sys->mem_offset);
return 1;
}
static struct pci_ops cns3xxx_pcie_ops = {
.read = cns3xxx_pci_read_config,
.write = cns3xxx_pci_write_config,
};
static int cns3xxx_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
struct cns3xxx_pcie *cnspci = pdev_to_cnspci(dev);
int irq = cnspci->irqs[slot];
pr_info("PCIe map irq: %04d:%02x:%02x.%02x slot %d, pin %d, irq: %d\n",
pci_domain_nr(dev->bus), dev->bus->number, PCI_SLOT(dev->devfn),
PCI_FUNC(dev->devfn), slot, pin, irq);
return irq;
}
static struct cns3xxx_pcie cns3xxx_pcie[] = {
[0] = {
.cfg_bases = {
[CNS3XXX_HOST_TYPE] = {
.virtual = CNS3XXX_PCIE0_HOST_BASE_VIRT,
.pfn = __phys_to_pfn(CNS3XXX_PCIE0_HOST_BASE),
.length = SZ_16M,
.type = MT_DEVICE,
},
[CNS3XXX_CFG0_TYPE] = {
.virtual = CNS3XXX_PCIE0_CFG0_BASE_VIRT,
.pfn = __phys_to_pfn(CNS3XXX_PCIE0_CFG0_BASE),
.length = SZ_16M,
.type = MT_DEVICE,
},
[CNS3XXX_CFG1_TYPE] = {
.virtual = CNS3XXX_PCIE0_CFG1_BASE_VIRT,
.pfn = __phys_to_pfn(CNS3XXX_PCIE0_CFG1_BASE),
.length = SZ_16M,
.type = MT_DEVICE,
},
},
.res_io = {
.name = "PCIe0 I/O space",
.start = CNS3XXX_PCIE0_IO_BASE,
.end = CNS3XXX_PCIE0_IO_BASE + SZ_16M - 1,
.flags = IORESOURCE_IO,
},
.res_mem = {
.name = "PCIe0 non-prefetchable",
.start = CNS3XXX_PCIE0_MEM_BASE,
.end = CNS3XXX_PCIE0_MEM_BASE + SZ_16M - 1,
.flags = IORESOURCE_MEM,
},
.irqs = { IRQ_CNS3XXX_PCIE0_RC, IRQ_CNS3XXX_PCIE0_DEVICE, },
.hw_pci = {
.domain = 0,
.nr_controllers = 1,
.ops = &cns3xxx_pcie_ops,
.setup = cns3xxx_pci_setup,
.map_irq = cns3xxx_pcie_map_irq,
},
},
[1] = {
.cfg_bases = {
[CNS3XXX_HOST_TYPE] = {
.virtual = CNS3XXX_PCIE1_HOST_BASE_VIRT,
.pfn = __phys_to_pfn(CNS3XXX_PCIE1_HOST_BASE),
.length = SZ_16M,
.type = MT_DEVICE,
},
[CNS3XXX_CFG0_TYPE] = {
.virtual = CNS3XXX_PCIE1_CFG0_BASE_VIRT,
.pfn = __phys_to_pfn(CNS3XXX_PCIE1_CFG0_BASE),
.length = SZ_16M,
.type = MT_DEVICE,
},
[CNS3XXX_CFG1_TYPE] = {
.virtual = CNS3XXX_PCIE1_CFG1_BASE_VIRT,
.pfn = __phys_to_pfn(CNS3XXX_PCIE1_CFG1_BASE),
.length = SZ_16M,
.type = MT_DEVICE,
},
},
.res_io = {
.name = "PCIe1 I/O space",
.start = CNS3XXX_PCIE1_IO_BASE,
.end = CNS3XXX_PCIE1_IO_BASE
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