// SPDX-License-Identifier: (GPL-2.0+ OR MIT)#include<dt-bindings/gpio/gpio.h>#include<dt-bindings/interrupt-controller/irq.h>#include<dt-bindings/interrupt-controller/arm-gic.h>#include<dt-bindings/pinctrl/rockchip.h>#include<dt-bindings/clock/rk3228-cru.h>#include<dt-bindings/thermal/thermal.h>/{#address-cells=<1>;#size-cells=<1>;interrupt-parent=<&gic>;aliases{serial0=&uart0;serial1=&uart1;serial2=&uart2;spi0=&spi0;};cpus{#address-cells=<1>;#size-cells=<0>;cpu0:cpu@f00{device_type="cpu";compatible="arm,cortex-a7";reg=<0xf00>;resets=<&cruSRST_CORE0>;operating-points-v2=<&cpu0_opp_table>;#cooling-cells=<2>;/* min followed by max */clock-latency=<40000>;clocks=<&cruARMCLK>;enable-method="psci";};cpu1:cpu@f01{device_type="cpu";compatible="arm,cortex-a7";reg=<0xf01>;resets=<&cruSRST_CORE1>;operating-points-v2=<&cpu0_opp_table>;#cooling-cells=<2>;/* min followed by max */enable-method="psci";};cpu2:cpu@f02{device_type="cpu";compatible="arm,cortex-a7";reg=<0xf02>;resets=<&cruSRST_CORE2>;operating-points-v2=<&cpu0_opp_table>;#cooling-cells=<2>;/* min followed by max */enable-method="psci";};cpu3:cpu@f03{device_type="cpu";compatible="arm,cortex-a7";reg=<0xf03>;resets=<&cruSRST_CORE3>;operating-points-v2=<&cpu0_opp_table>;#cooling-cells=<2>;/* min followed by max */enable-method="psci";};};cpu0_opp_table:opp_table0{compatible="operating-points-v2";opp-shared;opp-408000000{opp-hz=/bits/64 <408000000>;opp-microvolt=<950000>;clock-latency-ns=<40000>;opp-suspend;};opp-600000000{opp-hz=/bits/64 <600000000>;opp-microvolt=<975000>;};opp-816000000{opp-hz=/bits/64 <816000000>;opp-microvolt=<1000000>;};opp-1008000000{opp-hz=/bits/64 <1008000000>;opp-microvolt=<1175000>;};opp-1200000000{opp-hz=/bits/64 <1200000000>;opp-microvolt=<1275000>;};};amba{compatible="simple-bus";#address-cells