// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2013 MundoReader S.L.
* Author: Heiko Stuebner <heiko@sntech.de>
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/clock/rk3188-cru.h>
#include <dt-bindings/power/rk3188-power.h>
#include "rk3xxx.dtsi"
/ {
compatible = "rockchip,rk3188";
cpus {
#address-cells = <1>;
#size-cells = <0>;
enable-method = "rockchip,rk3066-smp";
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a9";
next-level-cache = <&L2>;
reg = <0x0>;
clock-latency = <40000>;
clocks = <&cru ARMCLK>;
operating-points-v2 = <&cpu0_opp_table>;
resets = <&cru SRST_CORE0>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a9";
next-level-cache = <&L2>;
reg = <0x1>;
operating-points-v2 = <&cpu0_opp_table>;
resets = <&cru SRST_CORE1>;
};
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a9";
next-level-cache = <&L2>;
reg = <0x2>;
operating-points-v2 = <&cpu0_opp_table>;
resets = <&cru SRST_CORE2>;
};
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a9";
next-level-cache = <&L2>;
reg = <0x3>;
operating-points-v2 = <&cpu0_opp_table>;
resets = <&cru SRST_CORE3>;
};
};
cpu0_opp_table: opp_table0 {
compatible = "operating-points-v2";
opp-shared;
opp-312000000 {
opp-hz = /bits/ 64 <312000000>;
opp-microvolt = <875000>;
clock-latency-ns = <40000>;
};
opp-504000000 {
opp-hz = /bits/ 64 <504000000>;
opp-microvolt = <925000>;
};
opp-600000000 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <950000>;
opp-suspend;
};
opp-816000000 {
opp-hz = /bits/ 64 <816000000>;
opp-microvolt = <975000>;
};
opp-1008000000 {
opp-hz = /bits/ 64 <1008000000>;
opp-microvolt = <1075000>;
};
opp-1200000000 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <1150000>;
};
opp-1416000000 {
opp-hz = /bits/ 64 <1416000000>;
opp-microvolt = <1250000>;
};
opp-1608000000 {
opp-hz = /bits/ 64 <1608000000>;
opp-microvolt = <1350000>;
};
};
display-subsystem {
compatible = "rockchip,display-subsystem";
ports = <&vop0_out>, <&vop1_out>;
};
sram: sram@10080000 {
compatible = "mmio-sram";
reg = <0x10080000 0x8000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x10080000 0x8000>;
smp-sram@0 {
compatible = "rockchip,rk3066-smp-sram";
reg = <0x0 0x50>;
};
};
vop0: vop@1010c000 {
compatible = "rockchip,rk3188-vop";
reg = <0x1010c000 0x1000>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_LCDC0>, <&cru DCLK_LCDC0>, <&cru HCLK_LCDC0>;
clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
power-domains = <&power RK3188_PD_VIO>;
resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
reset-names = "axi", "ahb", "dclk";
status = "disabled";
vop0_out: port {
#address-cells = <1>;
#size-cells = <0>;
};
};
vop1: vop@1010e000 {
compatible = "rockchip,rk3188-vop";
reg = <0x1010e000 0x1000>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_LCDC1>, <&cru DCLK_LCDC1>, <&cru HCLK_LCDC1>;
clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
power-domains = <&power RK3188_PD_VIO>;
resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
reset-names = "axi", "ahb", "dclk";
status = "disabled";
vop1_out: port {
#address-cells = <1>;
#size-cells = <0>;
};
};
timer3: timer@2000e000 {
compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer";
reg = <0x2000e000 0x20>;
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_TIMER3>, <&cru PCLK_TIMER3>;
clock-names = "timer", "pclk";
};