/*
* DTS file for CSR SiRFmarco SoC
*
* Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
*
* Licensed under GPLv2 or later.
*/
/include/ "skeleton.dtsi"
/ {
compatible = "sirf,marco";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&gic>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <1>;
};
};
axi {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x40000000 0x40000000 0xa0000000>;
l2-cache-controller@c0030000 {
compatible = "sirf,marco-pl310-cache", "arm,pl310-cache";
reg = <0xc0030000 0x1000>;
interrupts = <0 59 0>;
arm,tag-latency = <1 1 1>;
arm,data-latency = <1 1 1>;
arm,filter-ranges = <0x40000000 0x80000000>;
};
gic: interrupt-controller@c0011000 {
compatible = "arm,cortex-a9-gic";
interrupt-controller;
#interrupt-cells = <3>;
reg = <0xc0011000 0x1000>,
<0xc0010100 0x0100>;
};
rstc-iobg {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0xc2000000 0xc2000000 0x1000000>;
rstc: reset-controller@c2000000 {
compatible = "sirf,marco-rstc";
reg = <0xc2000000 0x10000>;
#reset-cells = <1>;
};
};
sys-iobg {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0xc3000000 0xc3000000 0x1000000>;
clock-controller@c3000000 {
compatible = "sirf,marco-clkc";
reg = <0xc3000000 0x1000>;
interrupts = <0 3 0>;
};
rsc-controller@c3010000 {
compatible = "sirf,marco-rsc";
reg = <0xc3010000 0x1000>;
};
};
mem-iobg {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0xc4000000 0xc4000000 0x1000000>;
memory-controller@c4000000 {
compatible = "sirf,marco-memc";
reg = <0xc4000000 0x10000>;
interrupts = <0 27 0>;
};
};
disp-iobg0 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0xc5000000 0xc5000000 0x1000000>;
display0@c5000000 {
compatible = "sirf,marco-lcd";
reg = <0xc5000000 0x10000>;
interrupts = <0 30 0>;
};
vpp0@c5010000 {
compatible = "sirf,marco-vpp";
reg = <0xc5010000 0x10000>;
interrupts = <0 31 0>;
};
};
disp-iobg1 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0xc6000000 0xc6000000 0x1000000>;
display1@c6000000 {
compatible = "sirf,marco-lcd";
reg = <0xc6000000 0x10000>;
interrupts = <0 62 0>;
};
vpp1@c6010000 {
compatible = "sirf,marco-vpp";
reg = <0xc6010000 0x10000>;
interrupts = <0 63 0>;
};
};
graphics-iobg {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0xc8000000 0xc8000000 0x1000000>;
graphics@c8000000 {
compatible = "powervr,sgx540";
reg = <0xc8000000 0x1000000>;
interrupts = <0 6 0>;
};
};
multimedia-iobg {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0xc9000000 0xc9000000 0x1000000>;
multimedia@a0000000 {
compatible = "sirf,marco-video-codec";
reg = <0xc9000000 0x1000000>;
interrupts = <0 5 0>;
};
};
dsp-iobg {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0xca000000 0xca000000 0x2000000>;
dspif@ca000000 {
compatible = "sirf,marco-dspif";
reg = <0xca000000 0x10000>;
interrupts = <0 9 0>;
};
gps@ca010000 {
compatible = "sirf,marco-gps";
reg = <0xca010000 0x10000>;
interrupts = <0 7 0>;
};
dsp@cb000000 {
compatible = "sirf,marco-dsp";
reg = <0xcb000000 0x1000000>;
interrupts <