/*
* Copyright 2013 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include "imx6sl-pinfunc.h"
#include <dt-bindings/clock/imx6sl-clock.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
aliases {
ethernet0 = &fec;
gpio0 = &gpio1;
gpio1 = &gpio2;
gpio2 = &gpio3;
gpio3 = &gpio4;
gpio4 = &gpio5;
serial0 = &uart1;
serial1 = &uart2;
serial2 = &uart3;
serial3 = &uart4;
serial4 = &uart5;
spi0 = &ecspi1;
spi1 = &ecspi2;
spi2 = &ecspi3;
spi3 = &ecspi4;
usbphy0 = &usbphy1;
usbphy1 = &usbphy2;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <0x0>;
next-level-cache = <&L2>;
operating-points = <
/* kHz uV */
996000 1275000
792000 1175000
396000 975000
>;
fsl,soc-operating-points = <
/* ARM kHz SOC-PU uV */
996000 1225000
792000 1175000
396000 1175000
>;
clock-latency = <61036>; /* two CLK32 periods */
clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>,
<&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_CLK_PLL1_SW>,
<&clks IMX6SL_CLK_PLL1_SYS>;
clock-names = "arm", "pll2_pfd2_396m", "step",
"pll1_sw", "pll1_sys";
arm-supply = <®_arm>;
pu-supply = <®_pu>;
soc-supply = <®_soc>;
};
};
intc: interrupt-controller@00a01000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x00a01000 0x1000>,
<0x00a00100 0x100>;
interrupt-parent = <&intc>;
};
clocks {
#address-cells = <1>;
#size-cells = <0>;
ckil {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
};
osc {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
};
};
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
interrupt-parent = <&gpc>;
ranges;
ocram: sram@00900000 {
compatible = "mmio-sram";
reg = <0x00900000 0x20000>;
clocks = <&clks IMX6SL_CLK_OCRAM>;
};
L2: l2-cache@00a02000 {
compatible = "arm,pl310-cache";
reg = <0x00a02000 0x1000>;
interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
cache-unified;
cache-level = <2>;
arm,tag-latency = <4 2 3>;
arm,data-latency = <4 2 3>;
};
pmu {
compatible = "arm,cortex-a9-pmu";
interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
};
aips1: aips-bus@02000000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x02000000 0x100000>;
ranges;
spba: spba-bus@02000000 {
compatible = "fsl,spba-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x02000000 0x40000>;
ranges;
spdif: spdif@02004000 {
compatible = "fsl,imx6sl-spdif",
"fsl,imx35-spdif";
reg = <0x02004000 0x4000>;
interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&sdma 14 18 0>,
<&sdma 15 18 0>;
dma-names = "rx", "tx";
clocks = <&clks IMX6SL_CLK_SPDIF_GCLK>, <&clks IMX6SL_CLK_OSC>,
<&clks IMX6SL_CLK_SPDIF>,