summaryrefslogtreecommitdiffstats
path: root/arch/arm/boot/dts/imx6q.dtsi
blob: f024ef28b34b9373895dbbb913c475eebb33298a (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
/*
 * Copyright 2013 Freescale Semiconductor, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 */

#include "imx6q-pinfunc.h"
#include "imx6qdl.dtsi"

/ {
	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			reg = <0>;
			next-level-cache = <&L2>;
			operating-points = <
				/* kHz    uV */
				1200000 1275000
				996000  1250000
				792000  1150000
				396000  950000
			>;
			clock-latency = <61036>; /* two CLK32 periods */
			clocks = <&clks 104>, <&clks 6>, <&clks 16>,
				 <&clks 17>, <&clks 170>;
			clock-names = "arm", "pll2_pfd2_396m", "step",
				      "pll1_sw", "pll1_sys";
			arm-supply = <&reg_arm>;
			pu-supply = <&reg_pu>;
			soc-supply = <&reg_soc>;
		};

		cpu@1 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			reg = <1>;
			next-level-cache = <&L2>;
		};

		cpu@2 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			reg = <2>;
			next-level-cache = <&L2>;
		};

		cpu@3 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			reg = <3>;
			next-level-cache = <&L2>;
		};
	};

	soc {
		ocram: sram@00900000 {
			compatible = "mmio-sram";
			reg = <0x00900000 0x40000>;
			clocks = <&clks 142>;
		};

		aips-bus@02000000 { /* AIPS1 */
			spba-bus@02000000 {
				ecspi5: ecspi@02018000 {
					#address-cells = <1>;
					#size-cells = <0>;
					compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
					reg = <0x02018000 0x4000>;
					interrupts = <0 35 0x04>;
					clocks = <&clks 116>, <&clks 116>;
					clock-names = "ipg", "per";
					status = "disabled";
				};
			};

			iomuxc: iomuxc@020e0000 {
				compatible = "fsl,imx6q-iomuxc";

				ipu2 {
					pinctrl_ipu2_1: ipu2grp-1 {
						fsl,pins = <
							MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0x10
							MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15       0x10
							MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02        0x10
							MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03        0x10
							MX6QDL_PAD_DI0_PIN4__IPU2_DI0_PIN04        0x80000000
							MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00   0x10
							MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01   0x10
							MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02   0x10
							MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03   0x10
							MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04   0x10
							MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05   0x10
							MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06   0x10
							MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07   0x10
							MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08   0x10
							MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09   0x10
							MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10  0x10
							MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11  0x10
							MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12  0x10
							MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13  0x10
							MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14  0x10
							MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15  0x10
							MX6QDL_PAD_DISP0_DAT16__IPU2_DISP0_DATA16  0x10
							MX6QDL_PAD_DISP0_DAT17__IPU2_DISP0_DATA17  0x10
							MX6QDL_PAD_DISP0_DAT18__IPU2_DISP0_DATA18  0x10
							MX6QDL_PAD_DISP0_DAT19__IPU2_DISP0_DATA19  0x10
							MX6QDL_PAD_DISP0_DAT20__IPU2_DISP0_DATA20  0x10
							MX6QDL_PAD_DISP0_DAT21__IPU2_DISP0_DATA21  0x10
							MX6QDL_PAD_DISP0_DAT22__IPU2_DISP0_DATA22  0x10
							MX6QDL_PAD_DISP0_DAT23__IPU2_DISP0_DATA23  0x10
						>;
					};
				};
			};
		};

		sata: sata@02200000 {
			compatible = "fsl,imx6q-ahci";
			reg = <0x02200000 0x4000>;
			interrupts = <0 39 0x04>;
			clocks =  <&clks 154>, <&clks 187>, <&clks 105>;
			clock-names = "sata", "sata_ref", "ahb";
			status = "disabled";
		};

		ipu2: ipu@02800000 {
			#crtc-cells = <1>;
			compatible = "fsl,imx6q-ipu";
			reg = <0x02800000 0x400000>;
			interrupts = <0 8 0x4 0 7 0x4>;
			clocks = <&clks 133>, <&clks 134>, <&clks 137>;
			clock-names = "bus", "di0", "di1";
			resets = <&src 4>;
		};
	};
};

&ldb {
	clocks = <&clks 33>, <&clks 34>,
		 <&clks 39>, <&clks 40>, <&clks 41>, <&clks 42>,
		 <&clks 135>, <&clks 136>;
	clock-names = "di0_pll", "di1_pll",
		      "di0_sel", "di1_sel", "di2_sel", "di3_sel",
		      "di0", "di1";

	lvds-channel@0 {
		crtcs = <&ipu1 0>, <&ipu1 1>, <&ipu2 0>, <&ipu2 1>;
	};

	lvds-channel@1 {
		crtcs = <&ipu1 0>, <&ipu1 1>, <&ipu2 0>, <&ipu2 1>;
	};
};