// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
/ {
#address-cells = <1>;
#size-cells = <1>;
compatible = "marvell,dove";
model = "Marvell Armada 88AP510 SoC";
interrupt-parent = <&intc>;
aliases {
gpio0 = &gpio0;
gpio1 = &gpio1;
gpio2 = &gpio2;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
compatible = "marvell,pj4a", "marvell,sheeva-v7";
device_type = "cpu";
next-level-cache = <&l2>;
reg = <0>;
};
};
l2: l2-cache {
compatible = "marvell,tauros2-cache";
marvell,tauros2-cache-features = <0>;
};
gpu-subsystem {
compatible = "marvell,dove-gpu-subsystem";
cores = <&gpu>;
status = "disabled";
};
i2c-mux {
compatible = "i2c-mux-pinctrl";
#address-cells = <1>;
#size-cells = <0>;
i2c-parent = <&i2c>;
pinctrl-names = "i2c0", "i2c1", "i2c2";
pinctrl-0 = <&pmx_i2cmux_0>;
pinctrl-1 = <&pmx_i2cmux_1>;
pinctrl-2 = <&pmx_i2cmux_2>;
i2c0: i2c@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
};
i2c1: i2c@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
/* Requires pmx_i2c1 on i2c controller node */
status = "disabled";
};
i2c2: i2c@2 {
reg = <2>;
#address-cells = <1>;
#size-cells = <0>;
/* Requires pmx_i2c2 on i2c controller node */
status = "disabled";
};
};
mbus {
compatible = "marvell,dove-mbus", "marvell,mbus", "simple-bus";
#address-cells = <2>;
#size-cells = <1>;
controller = <&mbusc>;
pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256M MEM space */
pcie-io-aperture = <0xf2000000 0x00200000>; /* 2M I/O space */
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x0100000 /* MBUS regs 1M */
MBUS_ID(0xf0, 0x02) 0 0xf1800000 0x1000000 /* AXI regs 16M */
MBUS_ID(0x01, 0xfd) 0 0xf8000000 0x8000000 /* BootROM 128M */
MBUS_ID(0x03, 0x01) 0 0xc8000000 0x0100000 /* CESA SRAM 1M */
MBUS_ID(0x0d, 0x00) 0 0xf0000000 0x0100000>; /* PMU SRAM 1M */
pcie: pcie {
compatible = "marvell,dove-pcie";
status = "disabled";
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
msi-parent = <&intc>;
bus-range = <0x00 0xff>;
ranges = <0x82000000 0x0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x2000
0x82000000 0x0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x2000
0x82000000 0x1 0x0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 Mem */
0x81000000 0x1 0x0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 I/O */
0x82000000 0x2 0x0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 Mem */
0x81000000 0x2 0x0 MBUS_ID(0x08, 0xe0) 0 1 0>; /* Port 1.0 I/O */
pcie0: pcie@1 {
device_type = "pci";
status = "disabled";
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
reg = <0x0800 0 0 0 0>;
clocks = <&gate_clk 4>;
marvell,pcie-port = <0>;
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
0x81000000 0 0 0x81000000 0x1 0 1 0>;
bus-range = <0x00 0xff>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &intc 16>;
};
pcie1: pcie@2 {
device_type = "pci";
status = "disabled";
assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
reg = <0x1000 0 0 0 0>;
clocks = <&gate_clk 5>;
marvell,pcie-port = <1>;
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x8