// SPDX-License-Identifier: GPL-2.0
#include "bcm283x.dtsi"
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/soc/bcm2835-pm.h>
/ {
compatible = "brcm,bcm2711";
#address-cells = <2>;
#size-cells = <1>;
interrupt-parent = <&gicv2>;
reserved-memory {
#address-cells = <2>;
#size-cells = <1>;
ranges;
/*
* arm64 reserves the CMA by default somewhere in ZONE_DMA32,
* that's not good enough for the BCM2711 as some devices can
* only address the lower 1G of memory (ZONE_DMA).
*/
linux,cma {
compatible = "shared-dma-pool";
size = <0x2000000>; /* 32MB */
alloc-ranges = <0x0 0x00000000 0x40000000>;
reusable;
linux,cma-default;
};
};
soc {
/*
* Defined ranges:
* Common BCM283x peripherals
* BCM2711-specific peripherals
* ARM-local peripherals
*/
ranges = <0x7e000000 0x0 0xfe000000 0x01800000>,
<0x7c000000 0x0 0xfc000000 0x02000000>,
<0x40000000 0x0 0xff800000 0x00800000>;
/* Emulate a contiguous 30-bit address range for DMA */
dma-ranges = <0xc0000000 0x0 0x00000000 0x40000000>;
/*
* This node is the provider for the enable-method for
* bringing up secondary cores.
*/
local_intc: local_intc@40000000 {
compatible = "brcm,bcm2836-l1-intc";
reg = <0x40000000 0x100>;
};
gicv2: interrupt-controller@40041000 {
interrupt-controller;
#interrupt-cells = <3>;
compatible = "arm,gic-400";
reg = <0x40041000 0x1000>,
<0x40042000 0x2000>,
<0x40044000 0x2000>,
<0x40046000 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_HIGH)>;
};
avs_monitor: avs-monitor@7d5d2000 {
compatible = "brcm,bcm2711-avs-monitor",
"syscon", "simple-mfd";
reg = <0x7d5d2000 0xf00>;
thermal: thermal {
compatible = "brcm,bcm2711-thermal";
#thermal-sensor-cells = <0>;
};
};
dma: dma@7e007000 {
compatible = "brcm,bcm2835-dma";
reg = <0x7e007000 0xb00>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
/* DMA lite 7 - 10 */
<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "dma0",
"dma1",
"dma2",
"dma3",
"dma4",
"dma5",
"dma6",
"dma7",
"dma8",
"dma9",
"dma10";
#dma-cells = <1>;
brcm,dma-channel-mask = <0x07f5>;
};
pm: watchdog@7e100000 {
compatible = "brcm,bcm2835-pm", "brcm,bcm2835-pm-wdt";
#power-domain-cells = <1>;
#reset-cells = <1>;
reg = <0x7e100000 0x114>,
<0x7e00a000 0x24>,
<0x7ec11000 0x20>;
clocks = <&clocks BCM2835_CLOCK_V3D>,
<&clocks BCM2835_CLOCK_PERI_IMAGE>,
<&clocks BCM2835_CLOCK_H264>,
<&clocks BCM2835_CLOCK_ISP>;
clock-names = "v3d", "peri_image", "h264", "isp";
system-power-controller;
};
rng@7e104000 {
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
/* RNG is incompatible with brcm,bcm2835-rng */
status = "disabled";
};
uart2: serial@7e201400 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x7e201400 0x200>;
interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clocks BCM2835_CLOCK_UART>,
<&clocks BCM2835_CLOCK_VPU>;
clock-names = "uartclk", "apb_pclk";
arm,primecell-periphid = <0x00241011>;
status = "disabled";
};
uart3: serial@7e201600 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x7e201600 0x200>;
interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clocks BCM2835_CLOCK_UART>,
<&clocks BCM2835_CLOCK_VPU>;
clock-names = "uartclk", "apb_pclk";
arm,primecell-periphid = <0x00241011>;
status = "disabled";
};
uart4: serial@7e201800 {
compatible = "arm,pl011", "arm,primecell";
reg = <