/*
* Device Tree Source for AM43xx clock data
*
* Copyright (C) 2013 Texas Instruments, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
&scm_clocks {
sys_clkin_ck: sys_clkin_ck@40 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sysboot_freq_sel_ck>, <&crystal_freq_sel_ck>;
ti,bit-shift = <31>;
reg = <0x0040>;
};
crystal_freq_sel_ck: crystal_freq_sel_ck@40 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
ti,bit-shift = <29>;
reg = <0x0040>;
};
sysboot_freq_sel_ck: sysboot_freq_sel_ck@44e10040 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
ti,bit-shift = <22>;
reg = <0x0040>;
};
adc_tsc_fck: adc_tsc_fck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&sys_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
dcan0_fck: dcan0_fck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&sys_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
dcan1_fck: dcan1_fck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&sys_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
mcasp0_fck: mcasp0_fck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&sys_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
mcasp1_fck: mcasp1_fck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&sys_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
smartreflex0_fck: smartreflex0_fck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&sys_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
smartreflex1_fck: smartreflex1_fck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&sys_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
sha0_fck: sha0_fck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&sys_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
aes0_fck: aes0_fck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&sys_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
rng_fck: rng_fck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&sys_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
ehrpwm0_tbclk: ehrpwm0_tbclk@664 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&l4ls_gclk>;
ti,bit-shift = <0>;
reg = <0x0664>;
};
ehrpwm1_tbclk: ehrpwm1_tbclk@664 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&l4ls_gclk>;
ti,bit-shift = <1>;
reg = <0x0664>;
};
ehrpwm2_tbclk: ehrpwm2_tbclk@664 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&l4ls_gclk>;
ti,bit-shift = <2>;
reg = <0x0664>;
};
ehrpwm3_tbclk: ehrpwm3_tbclk@664 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&l4ls_gclk>;
ti,bit-shift = <4>;
reg = <0x0664>;
};
ehrpwm4_tbclk: ehrpwm4_tbclk@664 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&l4ls_gclk>;
ti,bit-shift = <5>;
reg = <0x0664>;
};
ehrpwm5_tbclk: ehrpwm5_tbclk@664 {
#clock-cells =