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/*
* linux/arch/alpha/kernel/core_t2.c
*
* Written by Jay A Estabrook (jestabro@amt.tay1.dec.com).
* December 1996.
*
* based on CIA code by David A Rusling (david.rusling@reo.mts.dec.com)
*
* Code common to all T2 core logic chips.
*/
#define __EXTERN_INLINE
#include <asm/io.h>
#include <asm/core_t2.h>
#undef __EXTERN_INLINE
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/sched.h>
#include <linux/init.h>
#include <asm/ptrace.h>
#include <asm/delay.h>
#include <asm/mce.h>
#include "proto.h"
#include "pci_impl.h"
/* For dumping initial DMA window settings. */
#define DEBUG_PRINT_INITIAL_SETTINGS 0
/* For dumping final DMA window settings. */
#define DEBUG_PRINT_FINAL_SETTINGS 0
/*
* By default, we direct-map starting at 2GB, in order to allow the
* maximum size direct-map window (2GB) to match the maximum amount of
* memory (2GB) that can be present on SABLEs. But that limits the
* floppy to DMA only via the scatter/gather window set up for 8MB
* ISA DMA, since the maximum ISA DMA address is 2GB-1.
*
* For now, this seems a reasonable trade-off: even though most SABLEs
* have less than 1GB of memory, floppy usage/performance will not
* really be affected by forcing it to go via scatter/gather...
*/
#define T2_DIRECTMAP_2G 1
#if T2_DIRECTMAP_2G
# define T2_DIRECTMAP_START 0x80000000UL
# define T2_DIRECTMAP_LENGTH 0x80000000UL
#else
# define T2_DIRECTMAP_START 0x40000000UL
# define T2_DIRECTMAP_LENGTH 0x40000000UL
#endif
/* The ISA scatter/gather window settings. */
#define T2_ISA_SG_START 0x00800000UL
#define T2_ISA_SG_LENGTH 0x00800000UL
/*
* NOTE: Herein lie back-to-back mb instructions. They are magic.
* One plausible explanation is that the i/o controller does not properly
* handle the system transaction. Another involves timing. Ho hum.
*/
/*
* BIOS32-style PCI interface:
*/
#define DEBUG_CONFIG 0
#if DEBUG_CONFIG
# define DBG(args) printk args
#else
# define DBG(args)
#endif
static volatile unsigned int t2_mcheck_any_expected;
static volatile unsigned int t2_mcheck_last_taken;
/* Place to save the DMA Window registers as set up by SRM
for restoration during shutdown. */
static struct
{
struct {
unsigned long wbase;
unsigned long wmask;
unsigned long tbase;
} window[2];
unsigned long hae_1;
unsigned long hae_2;
unsigned long hae_3;
unsigned long hae_4;
unsigned long hbase;
} t2_saved_config __attribute((common));
/*
* Given a bus, device, and function number, compute resulting
* configuration space address and setup the T2_HAXR2 register
* accordingly. It is therefore not safe to have concurrent
* invocations to configuration space access routines, but there
* really shouldn't be any need for this.
*
* Type 0:
*
* 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1
* 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
* | | |D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|0|
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
*
* 31:11 Device select bit.
* 10:8 Function number
* 7:2 Register number
*
* Type 1:
*
* 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1
* 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
* | | | | | | | | | | |B|B|B|B|B|B|B|B|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|1|
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
*
* 31:24 reserved
* 23:16 bus number (8 bits = 128 possible buses)
* 15:11 Device number (5 bits)
* 10:8 function number
* 7:2 register number
*
* Notes:
* The function number selects which function of a multi-function device
* (e.g., SCSI and Ethernet).
*
* The register selects a DWORD (32 bit) register offset. Hence it
* doesn't get shifted by 2 bits as we want to "drop" the bottom two
* bits.
*/
static int
mk_conf_addr(struct pci_bus *pbus, unsigned int device_fn, int where,
unsigned long *pci_addr, unsigned char *type1)
{
unsigned long addr;
u8 bus = pbus->number;
DBG(("mk_conf_addr(bus=%d, dfn=0x%x, where=0x%x,"
" addr=0x%lx, type1=0x%x)\n",
bus, device_fn, where, pci_addr, type1));
if (bus == 0) {
int device = device_fn >> 3;
/* Type 0 configuration cycle. */
if (device > 8) {
DBG(("mk_conf_addr: device (%d)>20, returning -1\n",
device));
return -1;
}
*type1 = 0;
addr = (0x0800L << device) | ((device_fn & 7) << 8) | (where);
} else {
/* Type 1 configuration cycle. */
*type1 = 1;
addr = (bus << 16) | (device_fn << 8) | (where);
}
*pci_addr = addr;
DBG(("mk_conf_addr: returning pci_addr 0x%lx\n", addr));
return 0;
}
/*
* NOTE: both conf_read() and conf_write() may set HAE_3 when needing
* to do type1 access. This is protected by the use of spinlock IRQ
* primitives in the wrapper functions pci_{read,write}_config_*()
* defined in drivers/pci/pci.c.
*/
static unsigned int
conf_read(unsigned long addr, unsigned char type1)
{
unsigned int value, cpu, taken;
unsigned long t2_cfg = 0;
cpu = smp_processor_id();
DBG(("conf_read(addr=0x%lx, type1=%d)\n", addr, type1));
/* If Type1 access, must set T2 CFG. */
if (type1) {
t2_cfg = *(vulp)T2_HAE_3 & ~0xc0000000UL;
*(vulp)T2_HAE_3 = 0x40000000UL | t2_cfg;
mb();
}
mb();
draina();
mcheck_expected(cpu) = 1;
mcheck_taken(cpu) = 0;
t2_mcheck_any_expected |= (1 << cpu);
mb();
/* Access configuration space. */
value = *(vuip)addr;
mb();
mb(); /* magic */
/* Wait for possible mcheck. Also, this lets other CPUs clear
their mchecks as well, as they can reliably tell when
another CPU is in the midst of handling a real mcheck via
the "taken" function. */
udelay(100);
if ((taken = mcheck_taken(cpu))) {
mcheck_taken(cpu) = 0;
t2_mcheck_last_taken |= (1 << cpu);
value = 0xffffffffU;
mb();
}
mcheck_expected(cpu) = 0;
t2_mcheck_any_expected = 0;
mb();
/* If Type1 access, must reset T2 CFG so normal IO space ops work. */
if (type1) {
*(vulp)T2_HAE_3 = t2_cfg;
mb();
}
return value;
}
static void
conf_write(unsigned long addr, unsigned int value, unsigned char type1)
{
unsigned int cpu, taken;
unsigned long t2_cfg = 0;
cpu = smp_processor_id();
/* If Type1 access, must set T2 CFG. */
if (type1) {
t2_cfg = *(vulp)T2_HAE_3 & ~0xc0000000UL;
*(vulp)T2_HAE_3 = t2_cfg | 0x40000000UL;
mb();
}
mb();
draina();
mcheck_expected(cpu) = 1;
mcheck_taken(cpu) = 0;
t2_mcheck_any_expected |= (1 << cpu);
mb();
/* Access configuration space. */
*(vuip)addr = value;
mb();
mb(); /* magic */
/* Wait for possible mcheck. Also, this lets other CPUs clear
their mchecks as well, as they can reliably tell when
this CPU is in the midst of handling a real mcheck via
the "taken" function. */
udelay(100);
if ((taken = mcheck_taken(cpu))) {
mcheck_taken(cpu) = 0;
t2_mcheck_last_taken |= (1 << cpu);
mb();
}
mcheck_expected(cpu) = 0;
t2_mcheck_any_expected = 0;
mb();
/* If Type1 access, must reset T2 CFG so normal IO space ops work. */
if (type1) {
*(vulp)T2_HAE_3 = t2_cfg;
mb();
}
}
static int
t2_read_config(struct pci_bus *bus, unsigned int devfn, int where,
int size, u32 *value)
{
unsigned long addr, pci_addr;
unsigned char type1;
int shift;
long mask;
if (mk_conf_addr(bus, devfn, where, &pci_addr, &type1))
return PCIBIOS_DEVICE_NOT_FOUND;
mask = (size - 1) * 8;
shift = (where & 3) * 8;
addr = (pci_addr << 5) + mask + T2_CONF;
*value = conf_read(addr, type1) >> (shift);
return PCIBIOS_SUCCESSFUL;
}
static
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